Octave-Band Four-Beam Antenna Arrays with Stable Beam Direction Fed by Broadband 4 × 4 Butler Matrix

A novel concept of four-beam antenna arrays operating in a one-octave frequency range that allows stable beam directions and beamwidths to be achieved is proposed. As shown, such radiation patterns can be obtained when radiating elements are appropriately spaced and fed by a broadband 4 × 4 Butler matrix with directional filters connected to its outputs. In this solution, broadband radiating elements are arranged in such a way that, for the lower and upper frequencies, two separate subarrays can be distinguished, each one consisting of identically arranged radiating elements. The subarrays are fed by a broadband Butler matrix at the output to which an appropriate feeding network based on directional filters is connected. These filters ensure smooth signal switching across the operational bandwidth between elements utilized at lower and higher frequency bands. Therefore, as shown, it is possible to control both beamwidths and beam directions of the resulting multi-beam antenna arrays. Moreover, two different concepts of the feeding network connected in between the Butler matrix and radiating elements for lowering the sidelobes are discussed. The theoretical analyses of the proposed antenna arrays are shown and confirmed by measurements of the developed two-antenna arrays consisting of eight and twelve radiating elements, operating in a 2–4 GHz frequency range.

FPGA Realization of the Reconfigurable Mesh Counting Algorithm

Pass transistor logic (PTL) is a circuit design technique wherein transistors are used as switches. The reconfigurable mesh (RM) is a model that exploits the power of PTLs signal switching, by enabling flexible bus connections in a grid of processing elements containing switches. RM algorithms have theoretical results proving that [Formula: see text] can speed up computations significantly. However, the RM assumes that the latency of broadcasting a signal through [Formula: see text] switches (bus length) is 1. This is an unrealistic assumption preventing physical realizations of the RM. We propose the restricted-RM (RRM) wherein the bus lengths are restricted to [Formula: see text], [Formula: see text]. We show that counting the number of 1-bits in an input of [Formula: see text] bits can be done in [Formula: see text] steps for [Formula: see text] by an [Formula: see text] RRM. An almost matching lower bound is presented, using a technique which adds to the few existing lower-bound techniques in this area. Finally, the algorithm was directly coded over an FPGA, outperforming an optimal tree of adders. This work presents an alternative way of counting, which is fundamental for summing, beating regular Boolean circuits for large numbers, where summing a vast amount of numbers is the basis of any accelerator in embedded systems such as neural-nets and streaming. a