Improvement of Fermi-Level Pinning and Contact Resistivity in Ti/Ge Contact Using Carbon Implantation

Effects of carbon implantation (C-imp) on the contact characteristics of Ti/Ge contact were investigated. The C-imp into Ti/Ge system was developed to reduce severe Fermi-level pinning (FLP) and to improve the thermal stability of Ti/Ge contact. The current density (J)-voltage (V) characteristics showed that the rectifying behavior of Ti/Ge contact into an Ohmic-like behavior with C-imp. The lowering of Schottky barrier height (SBH) indicated that the C-imp could mitigate FLP. In addition, it allows a lower specific contact resistivity (ρc) at the rapid thermal annealing (RTA) temperatures in a range of 450–600 °C. A secondary ion mass spectrometry (SIMS) showed that C-imp facilitates the dopant segregation at the interface. In addition, transmission electron microscopy (TEM) and electron energy loss spectroscopy (EELS) mapping showed that after RTA at 600 °C, C-imp enhances the diffusion of Ge atoms into Ti layer at the interface of Ti/Ge. Thus, carbon implantation into Ge substrate can effectively reduce FLP and improve contact characteristics.

Analysis of a Schottky Barrier MOSFET for Synaptic Device Using Hot Carrier Injection

In this paper, we analyze the hot carrier injection (HCI) in an asymmetric dual-gate structure with a metallic source/drain. We propose a program/erase scheme where HCI occurs on the source side of the body. Owing to the large resistance of the Schottky barrier used, a large electric field is formed around the Schottky barrier. Therefore, impact ionization occurs as the gate voltage is increased and hot carriers are injected into the source side, which is less influenced by the drain voltage. We also analyze the program and erase efficiency by adjusting the Schottky barrier height or by using dopant segregation technique. We expect a small amount of current to flow and great efficiency of the program/erase operations to use as a synaptic device.