Comparison of Interleaving Methods of Parallel Connected Three-Level Bi-Directional Converters

The voltage and current ripples in the three-level bi-directional converter (TLBC) can be reduced by an interleaving technique that controls a phase difference between the modules of power converter. On the other hand, the inductor current ripple in TLBC is increased due to the circulating current between the modules. In this paper, the effects of two interleaving methods on a two-phase TLBC, Z-type and N-type, are investigated and compared. In particular, capacitor current ripple, and voltage ripple are compared by two interleaving methods verified through Powersim (PSIM) simulation.

ThunderRW

As random walk is a powerful tool in many graph processing, mining and learning applications, this paper proposes an efficient in-memory random walk engine named ThunderRW. Compared with existing parallel systems on improving the performance of a single graph operation, ThunderRW supports massive parallel random walks. The core design of ThunderRW is motivated by our profiling results: common RW algorithms have as high as 73.1% CPU pipeline slots stalled due to irregular memory access, which suffers significantly more memory stalls than the conventional graph workloads such as BFS and SSSP. To improve the memory efficiency, we first design a generic step-centric programming model named Gather-Move-Update to abstract different RW algorithms. Based on the programming model, we develop the step interleaving technique to hide memory access latency by switching the executions of different random walk queries. In our experiments, we use four representative RW algorithms including PPR, DeepWalk, Node2Vec and MetaPath to demonstrate the efficiency and programming flexibility of ThunderRW. Experimental results show that ThunderRW outperforms state-of-the-art approaches by an order of magnitude, and the step interleaving technique significantly reduces the CPU pipeline stall from 73.1% to 15.0%.

Design and Simulation of High-Efficiency High Gain non Isolated Interleaved DC-DC Converter with Reduced Voltage Stress on the Devices

In this paper, a non-isolated two interleaved modified step up KY Converter is analyzed and designed, whose efficiency, the voltage conversion ratio is high. There are various types of non -isolated converters such as buck-boost, Cuk, SEPIC, ZETA converters, etc but the voltage gain of these converters is less compare to the proposed interleaved KY converters. The voltage gain, efficiency of the proposed converter is enhanced compared to the previous converters. The voltage stress on semi-conductor devices and the ripple in the input current is reduced because of this interleaving technique. Switches with low on-state resistance are used due to which the conduction losses are reduced. Steady-state analysis and the operating principle are studied in continuous conduction mode (CCM) at ideal conditions. Simulation is also carried out in MATLAB/Simulink for the proposed interleaved KY converter.