Real Time Implementation of Video Compression Based on DWT

In this paper highly efficient 3D Discrete Wavelet Transform architecture is designed and implemented on seven series FPGA. The throughput is analyzed and its performance matrices are compared with different video file format. Today top of the line high-end image and video consume huge amount of memory. The designed architecture of DWT based video compression is again executed in parallel processing mode and its execution time is tabulated demonstrates reduced the processing or execution time. This paper demonstrates the superiority of the designed architecture both in normal mode of execution and parallel processing mode of execution .We know that higher the throughput of the video processing design results in Low power consumption. The Internal Architecture of the design is explained in brief and is synthesized in Xilinx Vivado 17.4 and implemented on Zed board. Based on the experimental results of the design being implemented on FPGA, demonstrates the memory saving capabilities and superiority of this architecture. The resultant architecture has drastically reduced latency and has enhanced the speed of operation.

Novel DWT/IDWT Architecture for 3D with Nine Stage 2D Parallel Processing using Split Distributed Arithmetic

Novel high-speed memory optimized distributed arithmetic (DA)-based architecture is developed and modeled for 3D discrete wavelet transform (DWT). The memory requirement for the proposed architecture is designed to [Formula: see text] pixel dynamic memory space and [Formula: see text] ROM. The proposed 3D-DWT architecture implements 9/7 Daubechies wavelet filters, synthesizes 7127 bytes of memory for temporary storage and uses 758 adders, 36 multiplexers of 16:1 and 36 up counter to realize the 3D-DWT hardware. The 3D-DWT engine is implemented and tested in a Xilinx FPGA Vertex5 XC5VLX155T with high area and power efficiency. The maximum delay in the timing path is 2.676[Formula: see text]ns and the 3D-DWT works at maximum frequency of 381[Formula: see text]MHz clock.

Hierarchical Cubical Tensor Decomposition through Low Complexity Orthogonal Transforms

In this work, new approaches are proposed for the 3D decomposition of a cubical tensor of size N × N × N for N = 2n through hierarchical deterministic orthogonal transforms with low computational complexity, whose kernels are based on the Walsh-Hadamard Transform (WHT) and the Complex Hadamard Transform (CHT). On the basis of the symmetrical properties of the real and complex Walsh-Hadamard matrices are developed fast computational algorithms whose computational complexity is compared with that of the famous deterministic transforms: the 3D Fast Fourier Transform, the 3D Discrete Wavelet Transform and the statistical Hierarchical Tucker decomposition. The comparison results show the lower computational complexity of the offered algorithms. Additionally, they ensure the high energy concentration of the original tensor into a small number of coefficients of the so calculated transformed spectrum tensor. The main advantage of the proposed algorithms is the reduction of the needed calculations due to the low number of hierarchical levels compared to the significant number of iterations needed to achieve the required decomposition accuracy based on the statistical methods. The choice of the 3D hierarchical decomposition is defined by the requirements and limitations related to the corresponding application area.