On the Luminescence and Driving Force of Stacking Faults in 4H-SiC

Since it was determined that the formation and expansion of intrinsic stacking faults (SFs) induced a drift in the forward voltage (Vf) in 4H-SiC bipolar devices, significant effort has been made to understand the driving force causing SF motion as well as the various associated luminescence processes. The observation that annealing of faulted SiC devices and epilayers induced SF contraction and a recovery of the Vf drift enabled the studying of the impact of various parameters such as temperature, injection level and operation time upon SF motion, the Vf drift and luminescence within the same device. However, these observations in many cases contradicted the previously reported driving force models. Here we report on a basic driving force model explaining SF expansion in hexagonal SiC as well as discuss the observation of green luminescence from C-core partial dislocations bounding the SFs that may indicate an enhanced mobility of point defects within forward biased SiC pin diodes.

Temperature Dependence of Shockley Stacking Fault Expansion and Contraction in 4H-SiC p-i-n Diodes

The nucleation and expansion of Shockley stacking faults (SSFs) in 4H-SiC is known to induce an increase in the forward voltage drop (Vf) of bipolar devices such as pin diodes. However, recent annealing experiments have shown that SSFs can not only expand, but that low temperature annealing (210-7000C) induces a contraction of the SSFs that is coupled with a full and repeatable recovery of the Vf drift. Here we report that following extended periods of forward bias operation that the Vf drift of 10kV 4H-SiC pin diodes saturates, with the saturation Vf drift dropping with increasing stressing temperature. Upon reaching saturation, increases in temperature during forward bias operation at the same injection conditions also lead to a partial recovery of the Vf drift. Furthermore, the magnitude of this current-induced recovery is dependent upon the injection current, as reductions in the current cause a slower, but larger overall Vf drift recovery. All of these results clearly indicate that the current driving force models for SSF expansion are either incomplete or incorrect and that further efforts are required for a more complete understanding of SSF dynamics to be obtained.

High Current 6 kV 4H-SiC PiN Diodes for Power Module Switching Applications

Forward voltage (VF) drift, in which a 4H-SiC PiN diode suffers from an irreversible increase in VF under forward current flow, continues to inhibit commercialization of 4H-SiC PiN diodes. We present our latest efforts at fabricating high blocking voltage (6 kV), high current (up to 50 A) 4H-SiC PiN diodes with the best combination of reverse leakage current (IR), forward voltage at rated current (VF), and VF drift yields. We have achieved greater than 60% total die yield onwafer for 50 A diodes with a chip size greater than 0.7 cm2. A comparison of the temperature dependent conduction and switching characteristics between a 50 A/6 kV 4H-SiC PiN diode and a commercially available 60 A/4.5 kV Si PiN diode is also presented.

Techniques for Minimizing the Basal Plane Dislocation Density in SiC Epilayers to Reduce Vf Drift in SiC Bipolar Power Devices

Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to <10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The first low BPD technique employs a selective etch of the substrate prior to epilayer growth to create a near on-axis surface where BPDs intersect the substrate surface. The second low BPD technique employs lithographic and dry etch patterning of the substrate prior to epilayer growth. Both processes impede the propagation of BPDs into epilayers by preferentially converting BPDs into threading edge dislocations (TEDs) during the initial stages of epilayer growth. With these techniques, we routinely achieve Vf stability yields of up to 90% in devices with active areas from 0.006 to 1 cm2, implying that the utility of the processes is not limited by device size.

Do You Really Expect To Grow Epilayers On That? A Rationale For Growing Epilayers On Roughened Surfaces

We describe surface preparation and epilayer growth techniques that readily reduce the density of Vf drift inducing basal plane dislocations in epilayers to less than 10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The optimal process route requires etching the substrate surface prior to epilayer growth to enhance the natural conversion of basal plane dislocations into threading edge dislocations during epilayer growth. The surface of this relatively rough “conversion” epilayer is subsequently repolished prior to growing the device structure. We provide details on processing parameters and potential problems as well as describe devices produced using this low basal plane dislocation growth processes.

Development of Epitaxial SiC Processes Suitable for Bipolar Power Devices

We present a survey of the most important factors relating to an epitaxial SiC growth process that is suitable for bipolar power devices. During the last several years, we have advanced our hot-wall SiC epitaxial growth technology to the point that we can support the transition of bipolar power devices from demonstrations to applications. Two major concerns in developing a suitable epitaxial technology are epilayer uniformity and extended defect density. Our state-of-theart capability permits the realization of 1-cm2 area devices with exceptional yields. Another major concern is the stability of bipolar devices during forward conduction. We have developed proprietary substrate and epilayer preparation technologies that have essentially eliminated Vf drift as a significant barrier to the exploitation of SiC based bipolar devices.