Gate-Misalignment-Effect Related Capacitance Behavior of a 100nm Double-Gate FD SOI NMOS Device with n>sup<+>/sup</p>sup<+>/sup<Poly Top/Bottom Gate

2015 ◽

Vol 19 (1) ◽

pp. 163-168

Author(s):

Hakkee Jung

Keyword(s):

Gate Voltage ◽

Tunneling Current ◽

Double Gate ◽

Double Gate Mosfet ◽

Bottom Gate

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P‐1.14: The Influence of Bottom gate Dielectric Roughness on the Performance of Double‐Gate a‐IGZO Thin Film Transistors

SID Symposium Digest of Technical Papers ◽

10.1002/sdtp.13608 ◽

2019 ◽

Vol 50 (S1) ◽

pp. 677-680

Author(s):

Ludong Qin ◽

Xuan Deng ◽

Jinao Tao ◽

Shengdong Zhang

Keyword(s):

Thin Film ◽

Thin Film Transistors ◽

Gate Dielectric ◽

Double Gate ◽

Bottom Gate

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A Simple Method to Fabricate Double-Gate SOI MOSFET with Diffusion Layer on Bulk Silicon Wafer as the Bottom Gate

10.7567/ssdm.2001.c-4-4 ◽

2001 ◽

Author(s):

Xinnan Lin ◽

Chuguang Feng ◽

Shengdong Zhang ◽

Wai-Hung Ho ◽

Mansun Chan

Keyword(s):

Silicon Wafer ◽

Diffusion Layer ◽

Double Gate ◽

Bulk Silicon ◽

Simple Method ◽

Soi Mosfet ◽

Bottom Gate

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Bottom Gate Voltage Dependent Threshold Voltage Roll-off of Asymmetric Double Gate MOSFET

The Journal of the Korean Institute of Information and Communication Engineering ◽

10.6109/jkiice.2014.18.6.1422 ◽

2014 ◽

Vol 18 (6) ◽

pp. 1422-1428

Author(s):

Hakkee Jung

Keyword(s):

Threshold Voltage ◽

Gate Voltage ◽

Double Gate ◽

Double Gate Mosfet ◽

Voltage Dependent ◽

Bottom Gate

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Nitrided thermal SiO[sub 2] for use as top and bottom gate insulators in self-aligned double gate silicon-on-insulator metal–oxide–semiconductor field effect transistor

Journal of Vacuum Science & Technology B Microelectronics Processing and Phenomena ◽

10.1116/1.1364698 ◽

2001 ◽

Vol 19 (3) ◽

pp. 800 ◽

Cited By ~ 3

Author(s):

Shibly S. Ahmed ◽

John P. Denton ◽

Gerold W. Neudeck

Keyword(s):

Metal Oxide ◽

Field Effect ◽

Field Effect Transistor ◽

Metal Oxide Semiconductor ◽

Silicon On Insulator ◽

Oxide Semiconductor ◽

Double Gate ◽

Gate Insulators ◽

Effect Transistor ◽

Bottom Gate

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Unique capacitance phenomenon of a 100nm double-gate FD SOI NMOS device with n/sup +//p/sup +/ poly top/bottom gate

Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004. ◽

10.1109/icsict.2004.1434964 ◽

2005 ◽

Author(s):

C.P. Yang ◽

C.H. Hsu ◽

J.B. Kuo

Keyword(s):

Double Gate ◽

Bottom Gate

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Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-itisulator (SOI) NMOS devices using a compact model considering fringing electric field effect

The 11th IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications, 2003. EDMO 2003. ◽

10.1109/edmo.2003.1259988 ◽

2004 ◽

Author(s):

J.B. Kuo ◽

E.C. Sun ◽

M.T. Lin

Keyword(s):

Electric Field ◽

Threshold Voltage ◽

Field Effect ◽

Compact Model ◽

Electric Field Effect ◽

Double Gate ◽

Fully Depleted ◽

Misalignment Effect ◽

Fringing Electric Field

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2D analysis of bottom gate misalignment and process tolerant for sub-100 nm symmetric double-gate MOSFETs

2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668) ◽

10.1109/edssc.2003.1283514 ◽

2004 ◽

Cited By ~ 2

Author(s):

Jian Shen ◽

Tsz Yin Man ◽

Mansun Chan

Keyword(s):

Double Gate ◽

Bottom Gate

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Analysis of Tunneling Current of Asymmetric Double Gate MOSFET for Ratio of Top and Bottom Gate Oxide Film Thickness

The Journal of the Korean Institute of Information and Communication Engineering ◽

10.6109/jkiice.2016.20.5.992 ◽

2016 ◽

Vol 20 (5) ◽

pp. 992-997 ◽

Cited By ~ 1

Author(s):

Hakkee Jung

Keyword(s):

Oxide Film ◽

Film Thickness ◽

Tunneling Current ◽

Gate Oxide ◽

Double Gate ◽

Oxide Film Thickness ◽

Double Gate Mosfet ◽

Bottom Gate

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Subthreshold Swing for Top and Bottom Gate Voltage of Asymmetric Double Gate MOSFET

The Journal of the Korean Institute of Information and Communication Engineering ◽

10.6109/jkiice.2014.18.3.657 ◽

2014 ◽

Vol 18 (3) ◽

pp. 657-662

Author(s):

Hakkee Jung

Keyword(s):

Gate Voltage ◽

Subthreshold Swing ◽

Double Gate ◽

Double Gate Mosfet ◽

Bottom Gate

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Gate-Misalignment-Effect Related Capacitance Behavior of a 100nm Double-Gate FD SOI NMOS Device with n>sup/supsup/sup

Analysis of Tunneling Current for Bottom Gate Voltage of Sub-10 nm Asymmetric Double Gate MOSFET

P‐1.14: The Influence of Bottom gate Dielectric Roughness on the Performance of Double‐Gate a‐IGZO Thin Film Transistors

A Simple Method to Fabricate Double-Gate SOI MOSFET with Diffusion Layer on Bulk Silicon Wafer as the Bottom Gate

Bottom Gate Voltage Dependent Threshold Voltage Roll-off of Asymmetric Double Gate MOSFET

Nitrided thermal SiO[sub 2] for use as top and bottom gate insulators in self-aligned double gate silicon-on-insulator metal–oxide–semiconductor field effect transistor

Unique capacitance phenomenon of a 100nm double-gate FD SOI NMOS device with n/sup +//p/sup +/ poly top/bottom gate

Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-itisulator (SOI) NMOS devices using a compact model considering fringing electric field effect

2D analysis of bottom gate misalignment and process tolerant for sub-100 nm symmetric double-gate MOSFETs

Analysis of Tunneling Current of Asymmetric Double Gate MOSFET for Ratio of Top and Bottom Gate Oxide Film Thickness

Subthreshold Swing for Top and Bottom Gate Voltage of Asymmetric Double Gate MOSFET

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