Ultralow-Voltage Design of Nanometer CMOS Circuits for Smart Energy-Autonomous Systems

2012 ◽  
pp. 57-83
Author(s):  
David Bol
Keyword(s):  
Autonomous Systems ◽  
Cmos Circuits ◽  
Nanometer Cmos

Distributed ESD Protection System for Nanometer CMOS Circuits

2017 ◽  
Vol 19 (1) ◽  
pp. 60-64
Author(s):  
Yu. F. Adamov ◽  
◽  
E.S. Balaka ◽  
T. Yu. Isayeva ◽  
O. S. Matveyenko ◽  
...  
Keyword(s):  
Protection System ◽  
Cmos Circuits ◽  
Nanometer Cmos ◽  
Esd Protection

Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias

2013 ◽  
Author(s):  
Hector Villacorta ◽  
Jose Garcia-Gervacio ◽  
Victor Champac ◽  
Sebastia Bota ◽  
Jaime Martinez ◽  
...  
Keyword(s):  
Defect Detection ◽  
Cmos Circuits ◽  
Nanometer Cmos ◽  
Body Bias

Leakage Power Estimation of Adiabatic Circuits Using SPICE in Nanometer CMOS Processes

2010 ◽  
Vol 108-111 ◽  
pp. 625-630 ◽  
Author(s):  
Yang Bo Wu ◽  
Jian Ping Hu ◽  
Hong Li
Keyword(s):  
Significant Proportion ◽  
Power Estimation ◽  
Low Power Design ◽  
Leakage Power ◽  
Cmos Process ◽  
Cmos Circuits ◽  
Nanometer Cmos ◽  
Adiabatic Logic ◽  
Total Leakage ◽  
Pass Transistor

In deep sub-micro CMOS process, the leakage power is becoming a significant proportion in power dissipation. Hence, estimating the leakage power of CMOS circuits is very important in low-power design. In this paper, an estimation technology for the total leakage power of adiabatic logic circuits by using SPICE is proposed. The basic principle of power estimation for traditional CMOS circuits using SPICE is introduced. According to the energy dissipation characteristic of adiabatic circuits, the estimation technology for leakage power is discussed. Taken as an example, the estimation for total leakage power dissipations of PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits is illustrated using the proposed estimation technology.

Complementary Pass-Transistor Adiabatic Logic Using Dual Threshold CMOS Techniques

2010 ◽  
Vol 39 ◽  
pp. 55-60 ◽  
Author(s):  
Bin Bin Lu ◽  
Jian Ping Hu
Keyword(s):  
Energy Dissipation ◽  
Full Adder ◽  
Logic Circuits ◽  
Cmos Circuits ◽  
Technology Scaling ◽  
Nanometer Cmos ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Simulation Results ◽  
Scaling Down

With rapid technology scaling down, the energy dissipation of nanometer CMOS circuits is becoming a major concern, because of the increasing sub-threshold leakage in nanometer CMOS processes. This paper introduces a dual threshold CMOS (DTCMOS) technique for CPAL (complementary pass-transistor adiabatic logic) circuits to reduce sub-threshold leakage dissipations. The method to size the transistors of the dual-threshold CPAL gates is also discussed. A full adder using dual-threshold CPAL circuits is realized using 45nm BSIM4 CMOS model. HSPICE simulation results show that leakage dissipations of the CPAL full adder with DTCMOS techniques are reduced compared with the basic CPAL one.

Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits

2019 ◽  
Vol 35 (2) ◽  
pp. 163-172 ◽  
Author(s):  
Shuo Cai ◽  
Weizheng Wang ◽  
Fei Yu ◽  
Binyong He
Keyword(s):  
Cmos Circuits ◽  
Single Event ◽  
Single Event Transient ◽  
Nanometer Cmos

Analysis and optimization of nanometer CMOS circuits for soft-error tolerance

2006 ◽  
Vol 14 (5) ◽  
pp. 514-524 ◽  
Author(s):  
Y.S. Dhillon ◽  
A.U. Diril ◽  
A. Chatterjee ◽  
A.D. Singh
Keyword(s):  
Soft Error ◽  
Error Tolerance ◽  
Cmos Circuits ◽  
Nanometer Cmos
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