Systematic Design and Demonstration of Multi‐Bit Generation in Layered Materials Heterostructures Floating‐Gate Memory

2021 ◽  
pp. 2105472
Author(s):  
Oh Hun Gwon ◽  
Jong Yun Kim ◽  
Han Seul Kim ◽  
Seok‐Ju Kang ◽  
Hye Ryung Byun ◽  
...  
2021 ◽  
Vol 31 (43) ◽  
pp. 2170317
Author(s):  
Oh Hun Gwon ◽  
Jong Yun Kim ◽  
Han Seul Kim ◽  
Seok‐Ju Kang ◽  
Hye Ryung Byun ◽  
...  

2009 ◽  
Vol 48 (4) ◽  
pp. 04C153 ◽  
Author(s):  
Kosuke Ohara ◽  
Yukiharu Uraoka ◽  
Takashi Fuyuki ◽  
Ichiro Yamashita ◽  
Toshitake Yaegashi ◽  
...  

2021 ◽  
pp. 108062
Author(s):  
Maksym Paliy ◽  
Tommaso Rizzo ◽  
Piero Ruiu ◽  
Sebastiano Strangio ◽  
Giuseppe Iannaccone

Author(s):  
Sapan Agarwal ◽  
Diana Garland ◽  
John Niroula ◽  
Robin B. Jacobs-Gedrim ◽  
Alex Hsia ◽  
...  

2013 ◽  
Vol 24 (50) ◽  
pp. 505709 ◽  
Author(s):  
S Manna ◽  
R Aluguri ◽  
A Katiyar ◽  
S Das ◽  
A Laha ◽  
...  

2004 ◽  
Vol 830 ◽  
Author(s):  
P. Dimitrakis ◽  
P. Normand

ABSTRACTCurrent research directions and recent advances in the area of semiconductor nanocrystal floating-gate memory devices are herein reviewed. Particular attention is placed on the advantages, limitations and perspectives of some of the principal new alternatives suggested for improving device performance and reliability. The attractive option of generating Si nanocrystal memories by ion-beam-synthesis (IBS) is discussed with emphasis on the ultra-low-energy (ULE) regime. Pertinent issues related to the fabrication of low-voltage memory cells and the integration of the ULE-IBS technique in manufactory environment are discussed. The effect on device performance of parasitic transistors that form at the channel corner of shallow trench isolated transistors is described in details. It is shown that such parasitic transistors lead to a substantial degradation of the electrical properties of the intended devices and dominates the memory behavior of deep submicronic cells.


2021 ◽  
Author(s):  
Side Song ◽  
Guozhu Liu ◽  
Qi He ◽  
Xiang Gu ◽  
Genshen Hong ◽  
...  

Abstract In this paper, the combined effects of cycling endurance and radiation on floating gate memory cell are investigated in detail, the results indicate that: 1.The programmed flash cells with a prior appropriate number of program and erase cycling stress exhibit much smaller threshold voltage shift than their counterpart in response to radiation, which is mainly ascribed to the recombination of trapped electrons (introduced by cycling stress) and trapped holes (introduced by irradiation) in the oxide surrounding the floating gate; 2.The radiation induced transconductance degradation in prior cycled flash cell is more severe than those without cycling stress in both of the programmed state and erased state; 3. Radiation is more likely to induce interface generation in programmed state than in erased state. This paper will be useful in understanding the issues involved in cycling endurance and radiation effects as well as in designing radiation hardened floating gate memory cells.


2013 ◽  
Vol 50 (8) ◽  
pp. 281-287
Author(s):  
S. C. Lee ◽  
Q. Hu ◽  
J. Y. Lee ◽  
Y.-J. Baek ◽  
H. H. Lee ◽  
...  

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