Designing a multi‐layer full‐adder using a new three‐input majority gate based on quantum computing

Purpose In nano-scale-based very large scale integration technology, quantum-dot cellular automata (QCA) is considered as a strong and capable technology to replace the well-known complementary metal oxide semiconductor technology. In QCA technique, rotated majority gate (RMG) design is not explored greatly, and therefore, its advantages compared to original majority gate are unnoticed. This paper aims to provide a thorough observation at RMG gate with its capability to build robust circuits. Design/methodology/approach This paper presents a new methodology for structuring reliable 2n-bit full adder (FA) circuit design in QCA utilizing RMG. Mathematical proof is provided for RMG gate structure. A new 1-bit FA circuit design is projected here, which is constructed with RMG gate and clock-zone-based crossover approach in its configuration. Findings A new structure of a FA is projected in this paper. The proposed design uses only 50 number of QCA cells in its implementation with a latency of 3 clock zones. The proposed 1-bit FA design conception has been checked for its structure robustness by designing various 2, 4, 8, 16, 32 and 64-bit FA designs. The proposed FA designs save power from 46.87% to 25.55% at maximum energy dissipation of circuit level, 39.05% to 23.36% at average energy dissipation of circuit-level and 42.03% to 37.18% at average switching energy dissipation of circuit level. Originality/value This paper fulfills the gape of focused research for RMG with its detailed mathematical modeling analysis.

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Design of Efficient Full Adder in Quantum-Dot Cellular Automata

The Scientific World JOURNAL ◽

10.1155/2013/250802 ◽

2013 ◽

Vol 2013 ◽

pp. 1-10 ◽

Cited By ~ 36

Author(s):

Bibhash Sen ◽

Ayush Rajoria ◽

Biplab K. Sikdar

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

Full Adder ◽

Cmos Technology ◽

Digital Design ◽

Majority Gate ◽

Feature Size ◽

Quantum Dot Cellular Automata ◽

Potential Alternative ◽

High Level

Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.

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A Tunable Majority Gate-Based Full Adder Using Current-Induced Domain Wall Nanomagnets

IEEE Transactions on Magnetics ◽

10.1109/tmag.2016.2540600 ◽

2016 ◽

Vol 52 (8) ◽

pp. 1-7 ◽

Cited By ~ 22

Author(s):

Arman Roohi ◽

Ramtin Zand ◽

Ronald F. DeMara

Keyword(s):

Domain Wall ◽

Full Adder ◽

Majority Gate

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Performance evaluation of an efficient five input majority gate design in QCA nanotechnology

International Journal of Reconfigurable and Embedded Systems (IJRES) ◽

10.11591/ijres.v8.i3.pp194-205 ◽

2019 ◽

Vol 8 (3) ◽

pp. 194

Author(s):

Amanpreet Sandhu ◽

Sheifali Gupta

Keyword(s):

Energy Efficiency ◽

Performance Evaluation ◽

Power Dissipation ◽

Energy Efficient ◽

High Speed ◽

Clock Cycle ◽

Full Adder ◽

Majority Gate ◽

Quantum Dot Cellular Automata ◽

Gate Count

Quantum-dot-cellular-automata (QCA) is the imminent transistor less technology, considered at nano level with high speed of operation and lower power dissipation features. The present paper proposes a novel and an efficient 5-input coplanar majority gate (PMG) with improved structural and energy efficiency. The proposed gate consumes an occupational area of 0.01μm2 with 17 QCA cells which is 50% less in comparison to the best designs reported in literature. The proposed structure is also more energy efficient because it dissipates 21.1% less energy than the best reported designs. The correctness of a proposed majority gate is verified by designing a single bit full adder. The new 1-bit full adder design is structural efficient and robust in terms of gate count and clock delay. It consumes occupational area of 0.05μm2 with 58 QCA cells showing 16.6% improvement in structural efficiency as compared to the best design reported in. It is having a gate count of 4 with the delay of 1 clock cycle. Here, the QCADesigner and QCAPro tools are utilized for the simulation and energy dissipation analysis of proposed majority gate and full adder design.

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Controlled full adder or subtractor by vibrational quantum computing

Physical Review A ◽

10.1103/physreva.80.022332 ◽

2009 ◽

Vol 80 (2) ◽

Cited By ~ 10

Author(s):

L. Bomble ◽

D. Lauvergnat ◽

F. Remacle ◽

M. Desouter-Lecomte

Keyword(s):

Quantum Computing ◽

Full Adder

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An Ultra-Low-Power Five-Input Majority Gate in Quantum-Dot Cellular Automata

Journal of Circuits System and Computers ◽

10.1142/s0218126620501765 ◽

2020 ◽

Vol 29 (11) ◽

pp. 2050176

Author(s):

Feifei Deng ◽

Guangjun Xie ◽

Shaowei Wang ◽

Xin Cheng ◽

Yongqiang Zhang

Keyword(s):

Cellular Automata ◽

Power Consumption ◽

Low Power ◽

Power Dissipation ◽

Single Layer ◽

Full Adder ◽

Majority Gate ◽

Ultra Low Power ◽

Quantum Dot Cellular Automata ◽

Number Of Cells

Quantum-dot cellular automata (QCA) is a highly attractive alternative to CMOS for future digital circuit design, relying on its high-performance and low-power-consumption features. This paper analyzes and compares previously published five-input majority gates. These designs do not perform well in terms of physical properties, especially concerting power consumption. Therefore, an ultra-low-power five-input majority gate in one layer is proposed, which uses a minimum number of cells and smaller area, and achieves the expected highly polarized output compared with previous designs. In order to evaluate its practicability, a new one-bit coplanar full-adder is proposed. The analysis results show that this full-adder performs well compared with existing multilayer and single-layer designs. The number of cells of the proposed design is reduced by 7.14% to get the same area and clock delay compared with the best coplanar full-adder. In addition, its power dissipation is also reduced by 9.28% at 0.5[Formula: see text], 11.09% at 1[Formula: see text] and 12.66% at 1.5[Formula: see text] in terms of average energy dissipation compared with the best single-layer design. QCADesigner tool is used to verify the simulation results of the proposed designs and QCAPro tool is used to evaluate the power dissipation of all considered designs.

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