Performance evaluation of an efficient five input majority gate design in QCA nanotechnology

Quantum-dot-cellular-automata (QCA) is the imminent transistor less technology, considered at nano level with high speed of operation and lower power dissipation features. The present paper proposes a novel and an efficient 5-input coplanar majority gate (PMG) with improved structural and energy efficiency. The proposed gate consumes an occupational area of 0.01μm2 with 17 QCA cells which is 50% less in comparison to the best designs reported in literature. The proposed structure is also more energy efficient because it dissipates 21.1% less energy than the best reported designs. The correctness of a proposed majority gate is verified by designing a single bit full adder. The new 1-bit full adder design is structural efficient and robust in terms of gate count and clock delay. It consumes occupational area of 0.05μm2 with 58 QCA cells showing 16.6% improvement in structural efficiency as compared to the best design reported in. It is having a gate count of 4 with the delay of 1 clock cycle. Here, the QCADesigner and QCAPro tools are utilized for the simulation and energy dissipation analysis of proposed majority gate and full adder design.

Download Full-text

An Ultra-Low-Power Five-Input Majority Gate in Quantum-Dot Cellular Automata

Journal of Circuits System and Computers ◽

10.1142/s0218126620501765 ◽

2020 ◽

Vol 29 (11) ◽

pp. 2050176

Author(s):

Feifei Deng ◽

Guangjun Xie ◽

Shaowei Wang ◽

Xin Cheng ◽

Yongqiang Zhang

Keyword(s):

Cellular Automata ◽

Power Consumption ◽

Low Power ◽

Power Dissipation ◽

Single Layer ◽

Full Adder ◽

Majority Gate ◽

Ultra Low Power ◽

Quantum Dot Cellular Automata ◽

Number Of Cells

Quantum-dot cellular automata (QCA) is a highly attractive alternative to CMOS for future digital circuit design, relying on its high-performance and low-power-consumption features. This paper analyzes and compares previously published five-input majority gates. These designs do not perform well in terms of physical properties, especially concerting power consumption. Therefore, an ultra-low-power five-input majority gate in one layer is proposed, which uses a minimum number of cells and smaller area, and achieves the expected highly polarized output compared with previous designs. In order to evaluate its practicability, a new one-bit coplanar full-adder is proposed. The analysis results show that this full-adder performs well compared with existing multilayer and single-layer designs. The number of cells of the proposed design is reduced by 7.14% to get the same area and clock delay compared with the best coplanar full-adder. In addition, its power dissipation is also reduced by 9.28% at 0.5[Formula: see text], 11.09% at 1[Formula: see text] and 12.66% at 1.5[Formula: see text] in terms of average energy dissipation compared with the best single-layer design. QCADesigner tool is used to verify the simulation results of the proposed designs and QCAPro tool is used to evaluate the power dissipation of all considered designs.

Download Full-text

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) ◽

10.2174/2352096513666200107091932 ◽

2020 ◽

Vol 13 (6) ◽

pp. 864-870

Author(s):

Sai Venkatramana Prasada G.S ◽

G. Seshikala ◽

S. Niranjana

Keyword(s):

Low Power ◽

Power Dissipation ◽

High Speed ◽

High Performance ◽

Full Adder ◽

Fundamental Operation ◽

Wallace Tree ◽

Power Delay Product ◽

The Comparative Study ◽

Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

Download Full-text

Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique

Journal of Circuits System and Computers ◽

10.1142/s0218126615500942 ◽

2015 ◽

Vol 24 (07) ◽

pp. 1550094 ◽

Cited By ~ 2

Author(s):

Jizhong Shen ◽

Liang Geng ◽

Xuexiang Wu

Keyword(s):

Integrated Circuits ◽

Power Dissipation ◽

Energy Efficient ◽

Clock Cycle ◽

Control Technique ◽

Switching Activity ◽

Digital Integrated Circuits ◽

Flip Flop ◽

Deep Impact ◽

Power Pulse

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

Download Full-text

A Novel Approach to Design Area Optimized, Energy Efficient and High Speed Wallace-Tree Multiplier Using GDI Based Full Adder

2017 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC) ◽

10.1109/iccic.2017.8524324 ◽

2017 ◽

Author(s):

Korra Ravi Kumar

Keyword(s):

Energy Efficient ◽

High Speed ◽

Full Adder ◽

Wallace Tree ◽

Novel Approach ◽

Wallace Tree Multiplier

Download Full-text

Design and Analysis of High Speed Low Power Hybrid Adder Using Transmission Gates

International Journal of New Practices in Management and Engineering ◽

10.17762/ijnpme.v5i03.46 ◽

2016 ◽

Vol 5 (03) ◽

pp. 07-12

Author(s):

Prof. Amruta Bijwar

Keyword(s):

Power Dissipation ◽

High Speed ◽

Arithmetic Operation ◽

Vlsi Design ◽

Full Adder ◽

Basic Component ◽

Xnor Gate ◽

Transmission Gates ◽

Design Systems ◽

Complex Circuits

Addition is the vital arithmetic operation and it acts as a base for many arithmetic operations such as multipliers, dividers, etc. A full adder acts as a basic component in complex circuits. Full adder is the essential segment in many applications such as DSP, Microcontroller, Microprocessor, etc. There exists an inevitable swap between speed and power indulgence in VLSI design systems. A new modified hybrid 1-bit full adder using TG is presented. Here, the circuit is replaced with a simple XNOR gate, which increases the speed. Due to this, transistor count gets reduced results in better optimization of area. The analysis has been carried out also for 2, 4, 8 and 16 bit and it is compared with the various techniques. The result shows a significant improvement in speed, area, power dissipation and transistor counts.

Download Full-text

Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

International Journal for Research in Applied Science and Engineering Technology ◽

10.22214/ijraset.2021.37924 ◽

2021 ◽

Vol 9 (9) ◽

pp. 66-70

Author(s):

Nakul C. Kubsad

Keyword(s):

Power Dissipation ◽

High Speed ◽

Digital Signal ◽

Full Adder ◽

Digital Signal Processors ◽

Transmission Gate ◽

Logical Operations ◽

Recent Advancement ◽

Voltage Swing ◽

Signal Processors

Abstract: Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.

Download Full-text