Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines

2014 ◽  
Vol 43 (11) ◽  
pp. 1523-1540 ◽  
Author(s):  
D. Albano ◽  
M. Lanuzza ◽  
R. Taco ◽  
F. Crupi
Keyword(s):  
Analytical Modeling ◽  
Logic Circuits ◽  
Design Guidelines ◽  
Body Biasing ◽  
Subthreshold Logic

Design guidelines to achieve minimum energy operation for ultra low voltage tunneling FET logic circuits

2015 ◽  
Vol 54 (4S) ◽  
pp. 04DC04 ◽  
Author(s):  
Hiroshi Fuketa ◽  
Kazuaki Yoshioka ◽  
Koichi Fukuda ◽  
Takahiro Mori ◽  
Hiroyuki Ota ◽  
...  
Keyword(s):  
Low Voltage ◽  
Minimum Energy ◽  
Logic Circuits ◽  
Design Guidelines ◽  
Tunneling Fet

Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits

2013 ◽  
Vol 48 (8) ◽  
pp. 1986-1994 ◽  
Author(s):  
Hiroshi Fuketa ◽  
Ryo Takahashi ◽  
Makoto Takamiya ◽  
Masahiro Nomura ◽  
Hirofumi Shinohara ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Logic Circuits ◽  
Crosstalk Noise ◽  
Subthreshold Logic

Design Guidelines of Steep Subthreshold TFET to Minimize Energy of Logic Circuits

2014 ◽  
Author(s):  
H. Fuketa ◽  
K. Yoshioka ◽  
K. Fukuda ◽  
T. Mori ◽  
H. Ota ◽  
...  
Keyword(s):  
Logic Circuits ◽  
Design Guidelines

Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits

2010 ◽  
Vol E93-C (3) ◽  
pp. 332-339 ◽  
Author(s):  
Tadashi YASUFUKU ◽  
Taro NIIYAMA ◽  
Zhe PIAO ◽  
Koichi ISHIDA ◽  
Masami MURAKATA ◽  
...  
Keyword(s):  
Power Supply ◽  
Large Scale ◽  
Supply Voltage ◽  
Logic Circuits ◽  
Voltage Scaling ◽  
Power Supply Voltage ◽  
Supply Voltage Scaling ◽  
Subthreshold Logic
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