Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

2021 ◽  
Author(s):  
Erfan Abbasian ◽  
Morteza Gholipour
Keyword(s):  
Low Power ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory

A Low Power Static Random Access Memory Cell with High Read Stability

2012 ◽  
Vol 9 (8) ◽  
pp. 1049-1054 ◽  
Author(s):  
. Anurag-Bhargav ◽  
Shyam Akashe ◽  
Sanjay Sharma
Keyword(s):  
Low Power ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory

A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040010
Author(s):  
R. H. Gudlavalleti ◽  
B. Saman ◽  
R. Mays ◽  
Evan Heller ◽  
J. Chandy ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Quantum Well ◽  
Field Effect Transistors ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Input Gate ◽  
Reduction In Area

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.

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