Evaluation of trap states at front and back oxide interfaces and grain boundaries using electrical characteristic analysis and device simulation of polycrystalline silicon thin-film transistors

2005 ◽  
Vol 88 (2) ◽  
pp. 1-10 ◽  
Author(s):  
Mutsumi Kimura
Keyword(s):  
Thin Film ◽  
Grain Boundaries ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Electrical Characteristic ◽  
Device Simulation ◽  
Trap States ◽  
Characteristic Analysis ◽  
Silicon Thin Film ◽  
Oxide Interfaces

scholarly journals Device Simulation of Polycrystalline-Silicon Thin-Film Transistors with Trap States at Front and Back Oxide Interfaces

2004 ◽  
Vol 58 (9) ◽  
pp. 1242-1247
Author(s):  
Mutsumi Kimura ◽  
Tohru Yasuhara ◽  
Kiyoshi Harada ◽  
Daisuke Abe ◽  
Satoshi Inoue ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Device Simulation ◽  
Trap States ◽  
Silicon Thin Film ◽  
Oxide Interfaces

Extraction Technique of Trap Density at Grain Boundaries in Polycrystalline-Silicon Thin-Film Transistors with Device Simulation

2007 ◽  
Vol 46 (3B) ◽  
pp. 1308-1311 ◽  
Author(s):  
Kiyoshi Harada ◽  
Takuto Yoshino ◽  
Tohru Yasuhara ◽  
Mutsumi Kimura ◽  
Daisuke Abe ◽  
...  
Keyword(s):  
Thin Film ◽  
Grain Boundaries ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Device Simulation ◽  
Trap Density ◽  
Extraction Technique ◽  
Silicon Thin Film

EFFECT OF TRAP STATES AT THE OXIDE-SILICON INTERFACE IN POLYCRYSTALLINE SILICON THIN-FILM TRANSISTORS

2008 ◽  
Vol 22 (30) ◽  
pp. 5357-5364
Author(s):  
NAVNEET GUPTA
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
State Density ◽  
Trap States ◽  
Silicon Thin Film ◽  
Gate Oxide Thickness ◽  
Silicon Interface

This work presents the study of the effect of trap states at the oxide-silicon interface in lightly doped polycrystalline silicon thin-film transistors with large grains. In this study, it is assumed that the oxide-silicon interface traps are evenly distributed throughout the interface region and single grain boundary is present in the channel of poly-Si TFT. It is shown that improved device characteristics can be obtained by reducing the gate oxide thickness. It is also observed that as gate oxide thickness decreases for a constant value of trap state density in the oxide-silicon interface, the gate voltage required for channel formation is lowered and leads to a decrease in threshold voltage of the device. Calculated and experimental results are also found to be well consistent with each other.

Extraction of trap states in laser-crystallized polycrystalline-silicon thin-film transistors and analysis of degradation by self-heating

2002 ◽  
Vol 91 (6) ◽  
pp. 3855-3858 ◽  
Author(s):  
Mutsumi Kimura ◽  
Satoshi Inoue ◽  
Tatsuya Shimoda ◽  
Simon W.-B. Tam ◽  
O. K. Basil Lui ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Trap States ◽  
Silicon Thin Film ◽  
Self Heating

Carrier transport across grain boundaries in polycrystalline silicon thin film transistors

2016 ◽  
Vol 31 (1) ◽  
pp. 87-92 ◽  
Author(s):  
Yong Chen ◽  
Shuang Zhang ◽  
Zhang Li ◽  
Hanhua Huang ◽  
Wenfeng Wang ◽  
...  
Keyword(s):  
Thin Film ◽  
Grain Boundaries ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Carrier Transport ◽  
Silicon Thin Film
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