Device Simulation of Polycrystalline-Silicon Thin-Film Transistors with Trap States at Front and Back Oxide Interfaces

This work presents the study of the effect of trap states at the oxide-silicon interface in lightly doped polycrystalline silicon thin-film transistors with large grains. In this study, it is assumed that the oxide-silicon interface traps are evenly distributed throughout the interface region and single grain boundary is present in the channel of poly-Si TFT. It is shown that improved device characteristics can be obtained by reducing the gate oxide thickness. It is also observed that as gate oxide thickness decreases for a constant value of trap state density in the oxide-silicon interface, the gate voltage required for channel formation is lowered and leads to a decrease in threshold voltage of the device. Calculated and experimental results are also found to be well consistent with each other.

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Device Simulation of Grain Boundaries with Oxide-Silicon Interface Roughness in Laser-Crystallized Polycrystalline Silicon Thin-Film Transistors

Japanese Journal of Applied Physics ◽

10.1143/jjap.39.l775 ◽

2000 ◽

Vol 39 (Part 2, No. 8A) ◽

pp. L775-L778 ◽

Cited By ~ 6

Author(s):

Mutsumi Kimura ◽

Tsukasa Eguchi ◽

Satoshi Inoue ◽

Tatsuya Shimoda

Keyword(s):

Thin Film ◽

Grain Boundaries ◽

Thin Film Transistors ◽

Polycrystalline Silicon ◽

Device Simulation ◽

Interface Roughness ◽

Silicon Thin Film ◽

Silicon Interface

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Extraction of trap states in laser-crystallized polycrystalline-silicon thin-film transistors and analysis of degradation by self-heating

Journal of Applied Physics ◽

10.1063/1.1446238 ◽

2002 ◽

Vol 91 (6) ◽

pp. 3855-3858 ◽

Cited By ~ 23

Author(s):

Mutsumi Kimura ◽

Satoshi Inoue ◽

Tatsuya Shimoda ◽

Simon W.-B. Tam ◽

O. K. Basil Lui ◽

...

Keyword(s):

Thin Film ◽

Thin Film Transistors ◽

Polycrystalline Silicon ◽

Trap States ◽

Silicon Thin Film ◽

Self Heating

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Analytical Drain Current Model for Amorphous and Polycrystalline Silicon Thin-Film Transistors at Different Temperatures Considering Both Deep and Tail Trap States

2018 9th Inthernational Conference on Computer Aided Design for Thin-Film Transistors (CAD-TFT) ◽

10.1109/cad-tft.2018.8608111 ◽

2018 ◽

Author(s):

Hongyu He ◽

Yuan Liu ◽

Binghui Yan ◽

Xinnan Lin ◽

Xueren Zheng ◽

...

Keyword(s):

Thin Film ◽

Thin Film Transistors ◽

Polycrystalline Silicon ◽

Current Model ◽

Drain Current ◽

Trap States ◽

Silicon Thin Film ◽

Different Temperatures

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Abnormal Threshold Voltage Shifts in P-Channel Low-Temperature Polycrystalline Silicon Thin Film Transistors Under Negative Bias Temperature Stress

Journal of Nanoscience and Nanotechnology ◽

10.1166/jnn.2015.11167 ◽

2015 ◽

Vol 15 (10) ◽

pp. 7555-7558 ◽

Cited By ~ 1

Author(s):

Sang Sub Kim ◽

Pyung Ho Choi ◽

Do Hyun Baek ◽

Jae Hyeong Lee ◽

Byoung Deog Choi

Keyword(s):

Thin Film ◽

Low Temperature ◽

Threshold Voltage ◽

Thin Film Transistors ◽

Polycrystalline Silicon ◽

Charge Trapping ◽

Trap States ◽

Silicon Thin Film ◽

Threshold Voltage Shift ◽

Voltage Shift

In this research, we have investigated the instability of P-channel low-temperature polycrystalline silicon (poly-Si) thin-film transistors (LTPS TFTs) with double-layer SiO2/SiNX dielectrics. A negative gate bias temperature instability (NBTI) stress was applied and a turn-around behavior phenomenon was observed in the Threshold Voltage Shift (Vth). A positive threshold voltage shift occurs in the first stage, resulting from the negative charge trapping at the SiNX/SiO2 dielectric interface being dominant over the positive charge trapping at dielectric/Poly-Si interface. Following a stress time of 7000 s, the Vth switches to the negative voltage direction, which is “turn-around” behavior. In the second stage, the Vth moves from −1.63 V to −2 V, overwhelming the NBTI effect that results in the trapping of positive charges at the dielectric/Poly-Si interface states and generating grain-boundary trap states and oxide traps.

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