A new procedure for nonlinear statistical model extraction of GaAs FET-integrated circuits

This chapter looks at observed features of the cycle in a variety of time series. It sets out these features for the United States and a number of other countries, and then asks whether these features can be replicated by the use of a particular statistical model—a linear autoregression. For such linear models it is possible to broadly account for the observed features using moments of the series for growth rates, and this strategy is employed in the chapter. It then uses a particular nonlinear statistical model to see if it can match all the features, and further looks at two other nonlinear models first dealt with in Chapter 4. The chapter concludes with an examination of whether the binary indicators summarizing the recurrent states can be used in the context of standard multivariate methods such as vector autoregressions. This turns out not to be straightforward owing to the nature of the binary variables.

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A statistical model for determining the minimum size in integrated circuits

IEEE Transactions on Electron Devices ◽

10.1109/t-ed.1979.19391 ◽

1979 ◽

Vol 26 (2) ◽

pp. 135-142 ◽

Cited By ~ 14

Author(s):

J.T. Wallmark

Keyword(s):

Integrated Circuits ◽

Statistical Model ◽

Minimum Size

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Some applications of electron beam microanalysis techniques in VLSI process evaluation

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s042482010007463x ◽

1983 ◽

Vol 41 ◽

pp. 160-161

Author(s):

Simon Thomas

Keyword(s):

Integrated Circuits ◽

Process Evaluation ◽

Large Scale ◽

Technology Development ◽

Analytical Techniques ◽

Successful Implementation ◽

Analysis Of Failures ◽

Characterization Of Materials ◽

Circuits Vlsi

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.

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The study of interfacial reactions of nickel thin films on GaAs

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100074616 ◽

1983 ◽

Vol 41 ◽

pp. 156-157

Author(s):

L.J. Chen ◽

Y.F. Hsieh

Keyword(s):

Thin Films ◽

Integrated Circuits ◽

Interfacial Reactions ◽

Metal Contacts ◽

Nickel Thin Films ◽

Thin Foils ◽

The Status ◽

Si Doped ◽

Electron Microscopes

One measure of the maturity of a device technology is the ease and reliability of applying contact metallurgy. Compared to metal contact of silicon, the status of GaAs metallization is still at its primitive stage. With the advent of GaAs MESFET and integrated circuits, very stringent requirements were placed on their metal contacts. During the past few years, extensive researches have been conducted in the area of Au-Ge-Ni in order to lower contact resistances and improve uniformity. In this paper, we report the results of TEM study of interfacial reactions between Ni and GaAs as part of the attempt to understand the role of nickel in Au-Ge-Ni contact of GaAs.N-type, Si-doped, (001) oriented GaAs wafers, 15 mil in thickness, were grown by gradient-freeze method. Nickel thin films, 300Å in thickness, were e-gun deposited on GaAs wafers. The samples were then annealed in dry N2 in a 3-zone diffusion furnace at temperatures 200°C - 600°C for 5-180 minutes. Thin foils for TEM examinations were prepared by chemical polishing from the GaA.s side. TEM investigations were performed with JE0L- 100B and JE0L-200CX electron microscopes.

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