A study of network logic for wafer-scale parallel-access memory and a yield analysis

1995 ◽  
Vol 26 (2) ◽  
pp. 1-9
Author(s):  
Koichi Yamashita ◽  
Shohei Ikehara
Keyword(s):  
Access Memory ◽  
Yield Analysis ◽  
Wafer Scale ◽  
Parallel Access

Wafer-Scale Statistical Analysis of Graphene FETs—Part I: Wafer-Scale Fabrication and Yield Analysis

2017 ◽  
Vol 64 (9) ◽  
pp. 3919-3926 ◽  
Author(s):  
Anderson D. Smith ◽  
Stefan Wagner ◽  
Satender Kataria ◽  
B. Gunnar Malm ◽  
Max C. Lemme ◽  
...  
Keyword(s):  
Statistical Analysis ◽  
Yield Analysis ◽  
Wafer Scale

Wafer scale integration

1988 ◽  
Vol 135 (6) ◽  
pp. 281
Author(s):  
J.B. Butcher ◽  
K.K. Johnstone
Keyword(s):  
Wafer Scale ◽  
Wafer Scale Integration ◽  
Scale Integration

Investigation of Plasma Treatment Conditions for Wafer-Scale Room-Temperature Bonding Using Ultrathin Au Films in Ambient Air

2019 ◽  
Vol 139 (7) ◽  
pp. 217-218
Author(s):  
Michitaka Yamamoto ◽  
Takashi Matsumae ◽  
Yuichi Kurashima ◽  
Hideki Takagi ◽  
Tadatomo Suga ◽  
...  
Keyword(s):  
Plasma Treatment ◽  
Room Temperature ◽  
Ambient Air ◽  
Wafer Scale ◽  
Treatment Conditions

Device Selection for Failure Analysis of Chain Fails Using Diagnosis Driven Yield Analysis

2011 ◽  
Author(s):  
Chris Schuermyer ◽  
Brady Benware ◽  
Graham Rhodes ◽  
Davide Appello ◽  
Vincenzo Tancorre ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Yield Analysis ◽  
Analysis Methodology ◽  
Device Selection ◽  
Selection For ◽  
Random Defects

Abstract This work presents the first application of a diagnosis driven approach for identifying systematic chain fail defects in order to reduce the time spent in failure analysis. The zonal analysis methodology that is applied separates devices into systematic and random populations of chain fails in order to prevent submitting random defects for failure analysis. Two silicon case studies are presented to validate the production worthiness of diagnosis driven yield analysis for chain fails. The defects uncovered in these case studies are very subtle and would be difficult to identify with any other methodology.

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

1998 ◽  
Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Temperature Sensitive ◽  
Wafer Level ◽  
Top Down ◽  
Access Memory ◽  
Transmission Electron ◽  
Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

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