Device Selection for Failure Analysis of Chain Fails Using Diagnosis Driven Yield Analysis

2011 ◽  
Author(s):  
Chris Schuermyer ◽  
Brady Benware ◽  
Graham Rhodes ◽  
Davide Appello ◽  
Vincenzo Tancorre ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Yield Analysis ◽  
Analysis Methodology ◽  
Device Selection ◽  
Selection For ◽  
Random Defects

Abstract This work presents the first application of a diagnosis driven approach for identifying systematic chain fail defects in order to reduce the time spent in failure analysis. The zonal analysis methodology that is applied separates devices into systematic and random populations of chain fails in order to prevent submitting random defects for failure analysis. Two silicon case studies are presented to validate the production worthiness of diagnosis driven yield analysis for chain fails. The defects uncovered in these case studies are very subtle and would be difficult to identify with any other methodology.

Failure Analysis Methodology on Resistive Open Defects

2014 ◽  
Author(s):  
A.C.T. Quah ◽  
G.B. Ang ◽  
D. Nagalingam ◽  
C.Q. Chen ◽  
H.P. Ng ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Photon Emission ◽  
Analysis Methodology ◽  
Failure Path ◽  
Open Defect ◽  
Emission Microscopy ◽  
Open Defects ◽  
Logic Array ◽  
Failure Site

Abstract This paper describes the observation of photoemissions from saturated transistors along a connecting path with open defect in the logic array. By exploiting this characteristic phenomenon to distinguish open related issues, we described with 2 case studies using Photon Emission Microscopy, CAD navigation and layout tracing to identify the ‘open’ failure path. Further layout and EBAC analysis are then employed to effectively localize the failure site.

Failure Analysis for Inter-Level Short in Nanometer Semiconductor Technologies

2018 ◽  
Author(s):  
Zhigang Song
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Case Studies ◽  
Process Variation ◽  
Failure Mechanisms ◽  
Semiconductor Technology ◽  
New Materials ◽  
Analysis Methodology ◽  
Scaling Down ◽  
Nanometer Regime

Abstract As semiconductor technology keeps scaling down, plus new structures of transistor and new materials introduction, not only are new failure mechanisms introduced, but also old classic failure mechanisms get evolved. The obvious example of failure mechanism evolution is short defect. In the previous technologies, although short defects can happen in different layers and appear in different forms, they always happens at intra-level. As semiconductor technology advanced into nanometer regime, short defect no longer only happened in intra-level, but also more and more often happened in interlevel. Failure analysis on the inter-level short defects is much more challenging because they are usually due to interaction of two processes, such as process variation in two process steps at the same location, and often hide in the bottom of tapered and dense patterns. The conventional PFA (Physical Failure Analysis) methodology often misses discovering the defect and then the defect will be removed by subsequent polishing. This paper has demonstrated some methods to tackle the challenges with three case studies of such inter-level short defects in nanometer semiconductor technologies.

Lithium-ion Battery Degradation Mechanisms and Failure Analysis Methodology

2012 ◽  
Author(s):  
Bhanu Sood ◽  
Lucas Severn ◽  
Michael Osterman ◽  
Michael Pecht ◽  
Anton Bougaev ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Lithium Ion Batteries ◽  
Elevated Temperatures ◽  
Failure Process ◽  
Lithium Ion ◽  
Degradation Mechanisms ◽  
Analysis Methodology ◽  
Depth Of Discharge ◽  
Battery Degradation ◽  
Non Destructive

Abstract A review of the prevalent degradation mechanisms in Lithium ion batteries is presented. Degradation and eventual failure in lithium-ion batteries can occur for a variety of dfferent reasons. Degradation in storage occurs primarily due to the self-discharge mechanisms, and is accelerated during storage at elevated temperatures. The degradation and failure during use conditions is generally accelerated due to the transient power requirements, the high frequency of charge/discharge cycles and differences between the state-of-charge and the depth of discharge influence the degradation and failure process. A step-by-step methodology for conducting a failure analysis of Lithion batteries is presented. The failure analysis methodology is illustrated using a decision-tree approach, which enables the user to evaluate and select the most appropriate techniques based on the observed battery characteristics. The techniques start with non-destructive and non-intrusive steps and shift to those that are more destructive and analytical in nature as information about the battery state is gained through a set of measurements and experimental techniques.

Case Studies of Brittle Interfacial Failures in Area Array Solder Interconnects

2000 ◽  
Author(s):  
George M. Wenger ◽  
Richard J. Coyle ◽  
Patrick P. Solan ◽  
John K. Dorey ◽  
Courtney V. Dodd ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Failure Modes ◽  
Electroless Nickel ◽  
Electrical Performance ◽  
Printed Wiring Board ◽  
Solder Interconnects ◽  
Area Array ◽  
Surface Finishes ◽  
Soldering Reaction

Abstract A common pad finish on area array (BGA or CSP) packages and printed wiring board (PWB) substrates is Ni/Au, using either electrolytic or electroless deposition processes. Although both Ni/Au processes provide flat, solderable surface finishes, there are an increasing number of applications of the electroless nickel/immersion gold (ENi/IAu) surface finish in response to requirements for increased density and electrical performance. This increasing usage continues despite mounting evidence that Ni/Au causes or contributes to catastrophic, brittle, interfacial solder joint fractures. These brittle, interfacial fractures occur early in service or can be generated under a variety of laboratory testing conditions including thermal cycling (premature failures), isothermal aging (high temperature storage), and mechanical testing. There are major initiatives by electronics industry consortia as well as research by individual companies to eliminate these fracture phenomena. Despite these efforts, interfacial fractures associated with Ni/Au surface finishes continue to be reported and specific failure mechanisms and root cause of these failures remains under investigation. Failure analysis techniques and methodologies are crucial to advancing the understanding of these phenomena. In this study, the scope of the fracture problem is illustrated using three failure analysis case studies of brittle interfacial fractures in area array solder interconnects. Two distinct failure modes are associated with Ni/Au surface finishes. In both modes, the fracture surfaces appear to be relatively flat with little evidence of plastic deformation. Detailed metallography, scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), and an understanding of the metallurgy of the soldering reaction are required to avoid misinterpreting the failure modes.

Application of Conductive-AFM in Soft Failure Analysis

2017 ◽  
Author(s):  
Chuan Zhang ◽  
Yinzhe Ma ◽  
Gregory Dabney ◽  
Oh Chong Khiam ◽  
Esther P.Y. Chen
Keyword(s):  
Failure Analysis ◽  
Conductive Atomic Force Microscopy ◽  
Test Parameter ◽  
Conductive Afm ◽  
Force Microscopy ◽  
Analysis Methodology ◽  
Soft Failure ◽  
Atomic Force ◽  
Test Conditions ◽  
Sensitive Characteristics

Abstract Soft failures are among the most challenging yield detractors. They typically show test parameter sensitive characteristics, which would pass under certain test conditions but fail under other conditions. Conductive-atomic force microscopy (CAFM) emerged as an ideal solution for soft failure analysis that can balance the time and thoroughness. By inserting CAFM into the soft failure analysis flow, success rate of such type of analysis can be significantly enhanced. In this paper, a logic chain soft failure and a SRAM local bitline soft failure are used as examples to illustrate how this failure analysis methodology provides a powerful and efficient solution for soft failure analysis.

SEM-Based Nanoprobing on 40, 32 and 28 nm CMOS Devices Challenges for Semiconductor Failure Analysis

2013 ◽  
Author(s):  
Erik Paul ◽  
Holger Herzog ◽  
Sören Jansen ◽  
Christian Hobert ◽  
Eckhard Langer
Keyword(s):  
Electron Microscope ◽  
High Resolution ◽  
Scanning Electron Microscope ◽  
Failure Analysis ◽  
Case Studies ◽  
State Of The Art ◽  
Root Cause ◽  
Highly Efficient ◽  
Technology Nodes ◽  
Scanning Electron

Abstract This paper presents an effective device-level failure analysis (FA) method which uses a high-resolution low-kV Scanning Electron Microscope (SEM) in combination with an integrated state-of-the-art nanomanipulator to locate and characterize single defects in failing CMOS devices. The presented case studies utilize several FA-techniques in combination with SEM-based nanoprobing for nanometer node technologies and demonstrate how these methods are used to investigate the root cause of IC device failures. The methodology represents a highly-efficient physical failure analysis flow for 28nm and larger technology nodes.

Process Induced Defects in the Silicon Substrate: Approaches for Successful Failure Analysis

2010 ◽  
Author(s):  
J.G. van Hassel ◽  
Xiao-Mei Zhang
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Silicon Substrate ◽  
Processing Technique ◽  
Electrical Characteristics ◽  
Localization Method ◽  
The Right ◽  
Induced Defects

Abstract Failures induced in the silicon substrate by process marginalities or process mistakes need continuous attention in new as well as established technologies. Several case studies showing implant related defects and dislocations in silicon will be discussed. Depending on the electrical characteristics of the failure the localization method has to be chosen. The emphasis of the discussion will be on the importance of the right choice for further physical de-processing to reveal the defect. This paper focuses on the localization method, the de- processing technique and the use of Wright etch for subsequent TEM preparation.

Case Studies in Atomic Force Probe Analysis

2006 ◽  
Author(s):  
Randal Mulder ◽  
Sam Subramanian ◽  
Tony Chrastecky
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Light Emission ◽  
Electrical Characterization ◽  
Logic Circuits ◽  
Contrast Imaging ◽  
Atomic Force ◽  
Measuring Surface ◽  
Analysis Environment

Abstract The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.

Failure Analysis Enhancement by Incorporating a Compact Scan Diagnosis System

2014 ◽  
Author(s):  
Rommel Estores ◽  
Pascal Vercruysse ◽  
Karl Villareal ◽  
Eric Barbian ◽  
Ralph Sanchez ◽  
...  
Keyword(s):  
Data Analysis ◽  
Failure Analysis ◽  
Real Analysis ◽  
Failure Data ◽  
Analysis Methodology ◽  
Efficiency And Effectiveness ◽  
Scan Chain ◽  
On Chip ◽  
Analysis Environment ◽  
Selection Of

Abstract The failure analysis community working on highly integrated mixed signal circuitry is entering an era where simultaneously System-On-Chip technologies, denser metallization schemes, on-chip dissipation techniques and intelligent packages are being introduced. These innovations bring a great deal of defect accessibility challenges to the failure analyst. To contend in this era while aiming for higher efficiency and effectiveness, the failure analysis environment must undergo a disruptive evolution. The success or failure of an analysis will be determined by the careful selection of tools, data and techniques in the applied analysis flow. A comprehensive approach is required where hardware, software, data analysis, traditional FA techniques and expertise are complementary combined [1]. This document demonstrates this through the incorporation of advanced scan diagnosis methods in the overall analysis flow for digital functionality failures and supporting the enhanced failure analysis methodology. For the testing and diagnosis of the presented cases, compact but powerful scan test FA Lab hardware with its diagnosis software was used [2]. It can therefore easily be combined with the traditional FA techniques to provide stimulus for dynamic fault localizations [3]. The system combines scan chain information, failure data and layout information into one viewing environment which provides real analysis power for the failure analyst. Comprehensive data analysis is performed to identify failing cells/nets, provide a better overview of the failure and the interactions to isolate the fault further to a smaller area, or to analyze subtle behavior patterns to find and rationalize possible faults that are otherwise not detected. Three sample cases will be discussed in this document to demonstrate specific strengths and advantages of this enhanced FA methodology.

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