On Chip Inductors Design Flow

In this paper the authors present the concept and evaluation results of a complex GALS ASIC demonstrator in 40 nm CMOS process. This chip, named Moonrake, compares synchronous and GALS synchronization technology in a homogeneous experimental setting: same baseline designs, same manufacturing process, same die. The chip validates GALS technology for both point-to-point and network-centric on-chip communications, demonstrating its potentials for different applications. The design analysis, measurement and test results confirm the potential of GALS approach for the scaled technologies, showing the significant benefits in respect to area, power, and EMI when it comes to the complex system implementation. Furthermore, 91% of the tests performed on the GALS network-on-chip test structures completed successfully, validating the timing robustness of new area and latency-efficient synchronization schemes and proving that the design flow for GALS synchronization technology can be implemented by means of mainstream industrial tools.

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A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime

International Journal of Reconfigurable Computing ◽

10.1155/2009/942930 ◽

2009 ◽

Vol 2009 ◽

pp. 1-10 ◽

Cited By ~ 3

Author(s):

Thilo Pionteck ◽

Roman Koch ◽

Carsten Albrecht ◽

Erik Maehle

Keyword(s):

System Architecture ◽

Design Tool ◽

Design Flow ◽

Design Tools ◽

System Architectures ◽

Flexible System ◽

Reconfigurable System ◽

Communication Needs ◽

On Chip ◽

Architecture And Design

Runtime reconfigurable system-on-chip designs for FPGAs pose manifold demands on the underlying system architecture and design tool capabilities. The system architecture has to support varying communication needs of a changing number of processing units mapped onto diverse locations. Design tools should support an arbitrary placement of processing modules and the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules. While few works address the design of flexible system architectures, the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules is hardly ever considered due to design tool limitations. In this paper, a technique for circumventing this restriction is presented. It allows for a rededication of the reconfigurable area to a different number of individually sized reconfigurable regions. This technique is embedded in the design flow of a runtime reconfigurable system architecture for Xilinx Virtex-4 FPGAs. The system architecture will also be presented to provide a realistic application example.

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Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow

2012 International Conference on Reconfigurable Computing and FPGAs ◽

10.1109/reconfig.2012.6416763 ◽

2012 ◽

Cited By ~ 6

Author(s):

L. Gantel ◽

M.E.A Benkhelifa ◽

F. Lemonnier ◽

F. Verdier

Keyword(s):

Design Flow ◽

Reconfigurable Systems ◽

Systems On Chip ◽

On Chip

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On-chip measurements complementary to design flow for integrity in SoCs

2007 44th ACM/IEEE Design Automation Conference ◽

10.1145/1278480.1278583 ◽

2007 ◽

Cited By ~ 5

Author(s):

Makoto Nagata

Keyword(s):

Design Flow ◽

On Chip

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An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip

2007 Design, Automation & Test in Europe Conference & Exhibition ◽

10.1109/date.2007.364577 ◽

2007 ◽

Cited By ~ 35

Author(s):

Akash Kumar ◽

Andreas Hansson ◽

Jos Huisken ◽

Henk Corporaal

Keyword(s):

Design Flow ◽

Fpga Design ◽

Systems On Chip ◽

On Chip

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Quantitative comparison of performance analysis techniques for modular and generic network-on-chip

Advances in Radio Science ◽

10.5194/ars-7-107-2009 ◽

2009 ◽

Vol 7 ◽

pp. 107-112 ◽

Cited By ~ 3

Author(s):

M. C. Neuenhahn ◽

J. Schleifer ◽

H. Blume ◽

T. G. Noll

Keyword(s):

Performance Analysis ◽

Design Flow ◽

Cost Evaluation ◽

Design Stage ◽

Levels Of Abstraction ◽

Early Design Stage ◽

Analysis Techniques ◽

Implementation Costs ◽

Huge Impact ◽

On Chip

Abstract. NoC-specific parameters feature a huge impact on performance and implementation costs of NoC. Hence, performance and cost evaluation of these parameter-dependent NoC is crucial in different design-stages but the requirements on performance analysis differ from stage to stage. In an early design-stage an analysis technique featuring reduced complexity and limited accuracy can be applied, whereas in subsequent design-stages more accurate techniques are required. In this work several performance analysis techniques at different levels of abstraction are presented and quantitatively compared. These techniques include a static performance analysis using timing-models, a Colored Petri Net-based approach, VHDL- and SystemC-based simulators and an FPGA-based emulator. Conducting NoC-experiments with NoC-sizes from 9 to 36 functional units and various traffic patterns, characteristics of these experiments concerning accuracy, complexity and effort are derived. The performance analysis techniques discussed here are quantitatively evaluated and finally assigned to the appropriate design-stages in an automated NoC-design-flow.

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