CMOS Circuits for Full-custom and Analogue ICs

Harmonic and intermodulation performance of analogue CMOS circuits owing to mobility reduction

IEE Proceedings G Circuits Devices and Systems ◽

10.1049/ip-g-2.1991.0013 ◽

1991 ◽

Vol 138 (1) ◽

pp. 65

Author(s):

M.T. Abuelma'atti

Keyword(s):

Cmos Circuits ◽

Intermodulation Performance ◽

Mobility Reduction

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My-box representation for faulty CMOS circuits

IEE Proceedings G Circuits Devices and Systems ◽

10.1049/ip-g-2.1990.0034 ◽

1990 ◽

Vol 137 (3) ◽

pp. 225 ◽

Cited By ~ 1

Author(s):

J.-E. Chen ◽

C.L. Lee ◽

W.-Z. Shen

Keyword(s):

Cmos Circuits

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Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.1031 ◽

2009 ◽

Vol E92-A (4) ◽

pp. 1031-1038

Author(s):

Shiho HAGIWARA ◽

Takashi SATO ◽

Kazuya MASU

Keyword(s):

Cmos Circuits ◽

Path Delay ◽

Analytical Estimation ◽

Delay Variation

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A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.2764 ◽

2017 ◽

Vol E100.A (12) ◽

pp. 2764-2775 ◽

Cited By ~ 1

Author(s):

Jun SHIOMI ◽

Tohru ISHIHARA ◽

Hidetoshi ONODERA

Keyword(s):

Minimum Energy ◽

Cmos Circuits ◽

Sufficient Condition ◽

Necessary And Sufficient Condition ◽

Energy Point ◽

Threshold Voltages ◽

Necessary And Sufficient ◽

Minimum Energy Point

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CMOS circuits made in lamp-recrystallised silicon-on-insulator

Electronics Letters ◽

10.1049/el:19840204 ◽

1984 ◽

Vol 20 (7) ◽

pp. 298 ◽

Cited By ~ 1

Author(s):

D.P. Vu ◽

C. Leguet ◽

M. Haond ◽

D. Bensahel ◽

J.P. Colinge

Keyword(s):

Silicon On Insulator ◽

Cmos Circuits ◽

Made In

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Review on impact of nanoscale on CMOS circuits in VLSI design

10.1063/5.0058029 ◽

2021 ◽

Author(s):

Gajula Lakshminarayana ◽

S. Sribindu ◽

L. Suneel ◽

S. Gopala Krishna

Keyword(s):

Vlsi Design ◽

Cmos Circuits

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Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits

The Eighth IEEE European Test Workshop, 2003. Proceedings. ◽

10.1109/etw.2003.1231676 ◽

2004 ◽

Cited By ~ 4

Author(s):

E. Liau ◽

D. Schmitt-Landsiedel

Keyword(s):

Genetic Algorithm ◽

Neural Networks ◽

Power Supply ◽

Pattern Generation ◽

Cmos Circuits ◽

Switching Noise ◽

Worst Case

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LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS Circuits

Communications in Computer and Information Science - VLSI Design and Test ◽

10.1007/978-981-10-7470-7_44 ◽

2017 ◽

pp. 441-451 ◽

Cited By ~ 1

Author(s):

Ambika Prasad Shah ◽

Nandakishor Yadav ◽

Santosh Kumar Vishvakarma

Keyword(s):

Cmos Circuits ◽

Degradation Monitoring

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Modeling of Substrate Noise Effects in Dynamic CMOS Circuits

2008 IEEE Region 5 Conference ◽

10.1109/tpsd.2008.4562723 ◽

2008 ◽

Author(s):

Sagar. R. Gosavi ◽

Waleed K. Al-Assadi ◽

Sasikiran Burugapalli

Keyword(s):

Cmos Circuits ◽

Substrate Noise ◽

Noise Effects

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Generic linear RC delay modeling for digital CMOS circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.45868 ◽

1990 ◽

Vol 9 (4) ◽

pp. 367-376 ◽

Cited By ~ 32

Author(s):

A.-C. Deng ◽

Y.-C. Shiau

Keyword(s):

Cmos Circuits ◽

Digital Cmos ◽

Rc Delay

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