Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits

2004 ◽  
Author(s):  
E. Liau ◽  
D. Schmitt-Landsiedel
Keyword(s):  
Genetic Algorithm ◽  
Neural Networks ◽  
Power Supply ◽  
Pattern Generation ◽  
Cmos Circuits ◽  
Switching Noise ◽  
Worst Case

Power Supply Noise Analysis Using Neural Network and Genetic Algorithm Based on Automatic Test Equipment

2003 ◽  
Author(s):  
Eric Liau ◽  
Doris Schmitt-Landsiedel
Keyword(s):  
Genetic Algorithm ◽  
Power Supply ◽  
Noise Analysis ◽  
Test Equipment ◽  
Power Supply Noise ◽  
Automatic Test Equipment ◽  
Automatic Test ◽  
Worst Case ◽  
Novel Approach ◽  
Supply Noise

Abstract Power supply noise (PSN) is becoming more severe as technology scales, and can cause signal distortion and increase gate delay. This can further result in improper circuit operation. In this paper, we propose a novel approach based on ATE (automatic test equipment) that teaches neural networks (NN) to correctly classify a set of worst case input patterns with respect to the maximum instantaneous current. This can be thought of as a learning behavior of chip power consumption change due to different input patterns. Then a genetic algorithm (GA) was applied to further optimize this set of NN worst case patterns. A final set of worst case patterns were expected to detect a small critical sequence of high switching currents that was directly related to the worst case power supply noise. This novel diagnosis approach can efficiently identify the defective design or weakness due to PSN as well as locate the defect or weaknesses within the design.

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