Generalized Bidirectional Limited Magnitude Error Correcting Code for MLC Flash Memories

2017 ◽  
pp. 450-461
Author(s):  
Akram Hussain ◽  
Xinchun Yu ◽  
Yuan Luo
Keyword(s):  
Error Correcting Code ◽  
Flash Memories

Error correcting code for flash memories

2013 ◽  
Author(s):  
Anxiao Jiang ◽  
Yue Li ◽  
E. E. Gad ◽  
M. Langberg ◽  
J. Bruck
Keyword(s):  
Error Correcting Code ◽  
Flash Memories

Weighted Bit-Flipping Decoding of LDPC Codes with LLR Adjustment for MLC Flash Memories

2019 ◽  
Vol E102.A (11) ◽  
pp. 1571-1574
Author(s):  
Xuan ZHANG ◽  
Xiaopeng JIAO ◽  
Yu-Cheng HE ◽  
Jianjun MU
Keyword(s):  
Ldpc Codes ◽  
Flash Memories

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

Humidity reliability of commercial flash memories for long-term storage

2020 ◽  
Vol 59 (SL) ◽  
pp. SLLC01 ◽  
Author(s):  
Tomoki Murota ◽  
Toshiki Mimura ◽  
Ploybussara Gomasang ◽  
Shinji Yokogawa ◽  
Kazuyoshi Ueno
Keyword(s):  
Flash Memories ◽  
Long Term Storage ◽  
Term Storage

An error-correcting code framework for genetic sequence analysis

2004 ◽  
Vol 341 (1-2) ◽  
pp. 89-109 ◽  
Author(s):  
Elebeoba E. May ◽  
Mladen A. Vouk ◽  
Donald L. Bitzer ◽  
David I. Rosnick
Keyword(s):  
Sequence Analysis ◽  
Error Correcting Code ◽  
Genetic Sequence ◽  
Genetic Sequence Analysis

A Heavy-ion Beam Monitor Based on 3D NAND Flash Memories

2021 ◽  
pp. 1-1
Author(s):  
S. Gerardin ◽  
M. Bagatin ◽  
A. Paccagnella ◽  
S. Beltrami ◽  
A. Costantino ◽  
...  
Keyword(s):  
Ion Beam ◽  
Heavy Ion ◽  
Nand Flash ◽  
Flash Memories ◽  
Beam Monitor ◽  
Heavy Ion Beam

scholarly journals An Application of p-Fibonacci Error-Correcting Codes to Cryptography

Mathematics ◽  
2021 ◽  
Vol 9 (7) ◽  
pp. 789
Author(s):  
Emanuele Bellini ◽  
Chiara Marcolla ◽  
Nadir Murru
Keyword(s):  
Error Correcting Code ◽  
Error Correcting Codes ◽  
Multiparty Computation ◽  
Zero Knowledge ◽  
Signature Schemes ◽  
Standardization Process ◽  
Technology Standardization

In addition to their usefulness in proving one’s identity electronically, identification protocols based on zero-knowledge proofs allow designing secure cryptographic signature schemes by means of the Fiat–Shamir transform or other similar constructs. This approach has been followed by many cryptographers during the NIST (National Institute of Standards and Technology) standardization process for quantum-resistant signature schemes. NIST candidates include solutions in different settings, such as lattices and multivariate and multiparty computation. While error-correcting codes may also be used, they do not provide very practical parameters, with a few exceptions. In this manuscript, we explored the possibility of using the error-correcting codes proposed by Stakhov in 2006 to design an identification protocol based on zero-knowledge proofs. We showed that this type of code offers a valid alternative in the error-correcting code setting to build such protocols and, consequently, quantum-resistant signature schemes.

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