Collaborative Distributed Fault Simulation for Digital Electronic Circuits

Author(s):  
Eero Ivask ◽  
Sergei Devadze ◽  
Raimund Ubar
2011 ◽  
Vol 21 (05) ◽  
pp. 1323-1330 ◽  
Author(s):  
MINFANG PENG ◽  
JIAJIA WANG ◽  
CHI K. TSE ◽  
MEIE SHEN

Fault diagnosis has played an important role in the identification of fault mechanisms and the subsequent successful isolation of faults in electronic circuits. In this paper, we propose a novel procedure for fault diagnosis in analog circuits. We first generate a set of fault patterns from fault simulation, and our main task is to develop a practical description of the way in which these fault patterns interact. Our approach is based on the construction of a complex network that describes the inter-dependence of the various fault patterns. Analysis of this complex network shows that the degree distribution is scalefree-like and the connectivity is small-world. We henceforth identify a small number of fault patterns that are most highly connected (of highest degrees) with other fault patterns. Furthermore, we study the connection between this network of fault patterns and the original circuit, the purpose being to relate the information of the high-degree fault patterns with the physical circuit topology, thus allowing the physical fault locations and circuit elements to be identified. Our proposed approach will find applications in automatic fault diagnosis of large-scale electronic circuits.


Author(s):  
R. M. Anderson ◽  
T. M. Reith ◽  
M. J. Sullivan ◽  
E. K. Brandis

Thin films of aluminum or aluminum-silicon can be used in conjunction with thin films of chromium in integrated electronic circuits. For some applications, these films exhibit undesirable reactions; in particular, intermetallic formation below 500 C must be inhibited or prevented. The Al films, being the principal current carriers in interconnective metal applications, are usually much thicker than the Cr; so one might expect Al-rich intermetallics to form when the processing temperature goes out of control. Unfortunately, the JCPDS and the literature do not contain enough data on the Al-rich phases CrAl7 and Cr2Al11, and the determination of these data was a secondary aim of this work.To define a matrix of Cr-Al diffusion couples, Cr-Al films were deposited with two sets of variables: Al or Al-Si, and broken vacuum or single pumpdown. All films were deposited on 2-1/4-inch thermally oxidized Si substrates. A 500-Å layer of Cr was deposited at 120 Å/min on substrates at room temperature, in a vacuum system that had been pumped to 2 x 10-6 Torr. Then, with or without vacuum break, a 1000-Å layer of Al or Al-Si was deposited at 35 Å/s, with the substrates still at room temperature.


1991 ◽  
Vol 5 (1) ◽  
pp. 4 ◽  
Author(s):  
A.T. Johns
Keyword(s):  

2015 ◽  
Vol 19 (95) ◽  
pp. 272-275 ◽  
Author(s):  
Jo. Sterten ◽  
◽  
Andrej A. Verlan
Keyword(s):  

2020 ◽  
Vol 38 (3A) ◽  
pp. 446-456
Author(s):  
Bashar F. Midhat

Step down DC-DC converters are power electronic circuits, which mainly used to convert voltage from a level to a lower level. In this paper, a discontinuous controller is proposed as a control method in order to control Step-Down DC-DC converters. A Lyapunov stability criterion is used to mathematically prove the ability of the proposed controller to give the desired voltage. Simulationsl1 are performedl1 in MATLABl1 software. The simulationl1 resultsl1 are presentedl1 for changesl1 in referencel1 voltagel1 and inputl1 voltagel1 as well as stepl1 loadl1 variations. The resultsl1 showl1 the goodl1 performancel1 of the proposedl1 discontinuousl1 controller.


Author(s):  
Rommel Estores ◽  
Karo Vander Gucht

Abstract This paper discusses a creative manual diagnosis approach, a complementary technique that provides the possibility to extend Automatic Test Pattern Generation (ATPG) beyond its own limits. The authors will discuss this approach in detail using an actual case – a test coverage issue where user-generated ATPG patterns and the resulting ATPG diagnosis isolated the fault to a small part of the digital core. However, traditional fault localization techniques was unable to isolate the fault further. Using the defect candidates from ATPG diagnosis as a starting point, manual diagnosis through fault Injection and fault simulation was performed. Further fault localization was performed using the ‘not detected’ (ND) and/or ‘detected’ (DT) fault classes for each of the available patterns. The result has successfully deduced the defect candidates until the exact faulty net causing the electrical failure was identified. The ability of the FA lab to maximize the use of ATPG in combination with other tools/techniques to investigate failures in detail; is crucial in the fast root cause determination and, in case of a test coverage, aid in having effective test screen method implemented.


Author(s):  
Dan Bodoh ◽  
Anthony Blakely ◽  
Terry Garyet

Abstract Since failure analysis (FA) tools originated in the design-for-test (DFT) realm, most have abstractions that reflect a designer's viewpoint. These abstractions prevent easy application of diagnosis results in the physical world of the FA lab. This article presents a fault diagnosis system, DFS/FA, which bridges the DFT and FA worlds. First, it describes the motivation for building DFS/FA and how it is an improvement over off-the-shelf tools and explains the DFS/FA building blocks on which the diagnosis tool depends. The article then discusses the diagnosis algorithm in detail and provides an overview of some of the supporting tools that make DFS/FA a complete solution for FA. It also presents a FA example where DFS/FA has been applied. The example demonstrates how the consideration of physical proximity improves the accuracy without sacrificing precision.


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