Access Polynomial Based Self-healing Key Distribution with Improved Security and Performance

Author(s):  
Ratna Dutta
2021 ◽  
pp. 51371
Author(s):  
Yulong Wang ◽  
Yaqiong Li ◽  
Maoyong He ◽  
Jingjing Bai ◽  
Bingxiao Liu ◽  
...  

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Kadir Gümüş ◽  
Tobias A. Eriksson ◽  
Masahiro Takeoka ◽  
Mikio Fujiwara ◽  
Masahide Sasaki ◽  
...  

AbstractReconciliation is a key element of continuous-variable quantum key distribution (CV-QKD) protocols, affecting both the complexity and performance of the entire system. During the reconciliation protocol, error correction is typically performed using low-density parity-check (LDPC) codes with a single decoding attempt. In this paper, we propose a modification to a conventional reconciliation protocol used in four-state protocol CV-QKD systems called the multiple decoding attempts (MDA) protocol. MDA uses multiple decoding attempts with LDPC codes, each attempt having fewer decoding iteration than the conventional protocol. Between each decoding attempt we propose to reveal information bits, which effectively lowers the code rate. MDA is shown to outperform the conventional protocol in regards to the secret key rate (SKR). A 10% decrease in frame error rate and an 8.5% increase in SKR are reported in this paper. A simple early termination for the LDPC decoder is also proposed and implemented. With early termination, MDA has decoding complexity similar to the conventional protocol while having an improved SKR.


VLSI Design ◽  
2016 ◽  
Vol 2016 ◽  
pp. 1-17 ◽  
Author(s):  
Arezoo Kamran ◽  
Zainalabedin Navabi

More pronounced aging effects, more frequent early-life failures, and incomplete testing and verification processes due to time-to-market pressure in new fabrication technologies impose reliability challenges on forthcoming systems. A promising solution to these reliability challenges is self-test and self-reconfiguration with no or limited external control. In this work a scalable self-test mechanism for periodic online testing of many-core processor has been proposed. This test mechanism facilitates autonomous detection and omission of faulty cores and makes graceful degradation of the many-core architecture possible. Several test components are incorporated in the many-core architecture that distribute test stimuli, suspend normal operation of individual processing cores, apply test, and detect faulty cores. Test is performed concurrently with the system normal operation without any noticeable downtime at the application level. Experimental results show that the proposed test architecture is extensively scalable in terms of hardware overhead and performance overhead that makes it applicable to many-cores with more than a thousand processing cores.


2015 ◽  
Vol 10 (2) ◽  
pp. 221-237 ◽  
Author(s):  
P. Jesu Jayarin ◽  
J. Visumathi ◽  
R. Srilakshmi ◽  
Madhuri Pendyala

2010 ◽  
Vol 8 (6) ◽  
pp. 597-613 ◽  
Author(s):  
Ratna Dutta ◽  
Sourav Mukhopadhyay ◽  
Martin Collier

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