A Constant Loop Bandwidth Fraction-N Frequency Synthesizer for GNSS Receivers

Author(s):  
Dun Yan ◽  
Jiancheng Li ◽  
Xiaochen Gu ◽  
Songting Li ◽  
Chong Huang
2016 ◽  
Vol 8 (3) ◽  
pp. 302-307 ◽  
Author(s):  
Marijan Jurgo ◽  
Romualdas Navickas

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.


Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 109
Author(s):  
Youming Zhang ◽  
Xusheng Tang ◽  
Zhennan Wei ◽  
Kaiye Bao ◽  
Nan Jiang

This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.


2013 ◽  
Vol 850-851 ◽  
pp. 441-444
Author(s):  
Fei Yan Mu ◽  
Bao Sheng Ye ◽  
Jie Lin ◽  
Zhong Jian Kang

This paper designs an L-Band 1880-1980 MHz low spurious Multi-tuned frequency synthesizer. The frequency source utilizes a DDS to directly stimulate a PLL, which makes a balance between the DDS and the PLL complementary to each other, realizing better specifications. Meanwhile, in order to achieve better spurious suppression with wide loop bandwidth, a method based on triple tuned algorithm is introduced. This algorithm avoids the high level spurious components triggered by the DDS falling in PLL’s bandwidth, refining the structure of the DDS-directly-stimulating PLL circuit frequency lock time and spurious to improve performance. The simulation result shows that the frequency source achieves a frequency range of 1880MHz~1980MHz, a frequency resolution of 1MHz, a spur better than 80dBc, a phase noise of -103dBc/Hz@100kHz and a frequency lock time less than 2 μs.


2012 ◽  
Vol 21 (06) ◽  
pp. 1240010 ◽  
Author(s):  
XIAO PU ◽  
KRISHNASWAMY NAGARAJ ◽  
JACOB ABRAHAM ◽  
AXEL THOMSEN

A wide loop bandwidth in fractional-N PLL is desirable for good jitter performance. However, a wider bandwidth reduces the effective oversampling ratio between update rate and loop bandwidth, making quantization error a much bigger noise contributor. A successful implementation of a wideband frequency synthesizer is in managing jitter and spurious performance. In this paper we present a new PLL architecture for bandwidth extension. By using clock squaring buffers with built-in offsets, multiple clock edges are extracted from a single reference cycle and utilized for phase update, thereby effectively forming a reference multiplier. This enables a higher oversampling ratio for better quantization noise shaping and makes a wideband fractional-N PLL possible.


2014 ◽  
Vol 35 (1) ◽  
pp. 015004 ◽  
Author(s):  
Sen Li ◽  
Jinguang Jiang ◽  
Xifeng Zhou ◽  
Jianghua Liu

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