scholarly journals ANALYSIS OF FREQUENCY SYNTHESISERS FOR MULTISTANDART WIRELESS TRANSCEIVER / DAŽNIO SINTEZATORIŲ DAUGIASTANDARČIAMS BEVIELIO RYŠIO SIŲSTUVAMS IR IMTUVAMS ANALIZĖ

2016 ◽  
Vol 8 (3) ◽  
pp. 302-307 ◽  
Author(s):  
Marijan Jurgo ◽  
Romualdas Navickas
Keyword(s):  
Figure Of Merit ◽  
Frequency Synthesizer ◽  
Cmos Technology ◽  
Wireless Transceivers ◽  
Frequency Locking ◽  
Wireless Transceiver ◽  
Loop Bandwidth ◽  
Charge Pump Pll ◽  
Chip Size ◽  
Better Than

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

scholarly journals A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 109
Author(s):  
Youming Zhang ◽  
Xusheng Tang ◽  
Zhennan Wei ◽  
Kaiye Bao ◽  
Nan Jiang
Keyword(s):  
Phase Noise ◽  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Chip Area ◽  
Loop Bandwidth ◽  
Bandwidth Control ◽  
Ku Band

This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

An L-Band Low Spurious Multi-Tuned Frequency Synthesizer

2013 ◽  
Vol 850-851 ◽  
pp. 441-444
Author(s):  
Fei Yan Mu ◽  
Bao Sheng Ye ◽  
Jie Lin ◽  
Zhong Jian Kang
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Resolution ◽  
Frequency Range ◽  
Improve Performance ◽  
Loop Bandwidth ◽  
Spurious Suppression ◽  
Frequency Source ◽  
L Band ◽  
High Level ◽  
Better Than

This paper designs an L-Band 1880-1980 MHz low spurious Multi-tuned frequency synthesizer. The frequency source utilizes a DDS to directly stimulate a PLL, which makes a balance between the DDS and the PLL complementary to each other, realizing better specifications. Meanwhile, in order to achieve better spurious suppression with wide loop bandwidth, a method based on triple tuned algorithm is introduced. This algorithm avoids the high level spurious components triggered by the DDS falling in PLL’s bandwidth, refining the structure of the DDS-directly-stimulating PLL circuit frequency lock time and spurious to improve performance. The simulation result shows that the frequency source achieves a frequency range of 1880MHz～1980MHz, a frequency resolution of 1MHz, a spur better than 80dBc, a phase noise of -103dBc/Hz@100kHz and a frequency lock time less than 2 μs.

A LOW-PHASE-NOISE CMOS VCO FOR K-BAND APPLICATION

2013 ◽  
Vol 22 (06) ◽  
pp. 1350040
Author(s):  
MEI-LING YEH ◽  
YAO-CHIAN LIN ◽  
CHUNG-CHENG CHANG
Keyword(s):  
Phase Noise ◽  
Figure Of Merit ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Chip Size ◽  
High Figure ◽  
Low Phase Noise ◽  
Capacitive Feedback ◽  
Measured Phase ◽  
K Band

A new high figure-of-merit (FOM) and low-phase-noise 20.73-GHz voltage-controlled oscillator is designed for K-band applications in this paper. The capacitive feedback technique is used for the low-phase-noise VCO design. The VCO can be tuned from 20.817 GHz to 20.266 GHz. The measured phase noise is -115.57 dBc/Hz at 1 MHz offset from the carrier frequency. The corresponding FOM is calculated to be -190 dBc/Hz. The VCO is implemented with the TSMC 0.18 μm one-poly-six-metal 1.7 V mixed-signal/RF CMOS technology, and the chip size is 0.51 × 0.74 mm2.

Low Power, Wide Range Synthesizer for 534MHz–18.56GHz Band with FoM of −192.45dBc/Hz

2021 ◽  
pp. 2250032
Author(s):  
Gaurav Kumar Sharma ◽  
Arun Kishor Johar ◽  
D. Boolchandani
Keyword(s):  
Figure Of Merit ◽  
Satellite Communication ◽  
Frequency Synthesizer ◽  
Supply Voltage ◽  
Wide Spectrum ◽  
Charge Pump ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Loop Filter ◽  
Wide Range

A wide range frequency synthesizer is designed with the help of dual voltage tunable Differential Ring Oscillator (DRO). Frequency ranging from 534[Formula: see text]MHz to 18.56[Formula: see text]GHz can be generated using the proposed synthesizer. As proposed circuit utilizes dual voltage tunable DRO, a select input is provided to control the output frequency range. Logic low value (0[Formula: see text]V) of select input generates frequencies from 534[Formula: see text]MHz to 5.08[Formula: see text]GHz whereas logic high value (1.1[Formula: see text]V) of select input enables the frequency generation in the range of 5.08[Formula: see text]GHz to 18.56[Formula: see text]GHz. This work utilizes a single charge pump and single loop filter along with charge pump and bias control circuit. Proposed circuit is designed in GPDK 45-nm CMOS technology with supply voltage of 1.1[Formula: see text]V. Power consumption of the proposed circuits is 2.88[Formula: see text]mW while generating frequency of 7.84[Formula: see text]GHz. Proposed synthesizer demonstrates Figure of Merit (FoM2) of [Formula: see text][Formula: see text]dBc/Hz at this frequency. Because of such a wide spectrum, this synthesizer is well suited in the field of satellite communication, GPS and navigation.

scholarly journals An 18.8–33.9 GHz, 2.26 mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2551
Author(s):  
Kwang-Il Oh ◽  
Goo-Han Ko ◽  
Jeong-Geun Kim ◽  
Donghyun Baek
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Frequency Divider ◽  
Oxide Semiconductor ◽  
Center Frequency ◽  
Radar Sensor ◽  
Frequency Locking ◽  
Current Reuse ◽  
Sensor Applications ◽  
Locking Range

An 18.8–33.9 GHz, 2.26 mW current-reuse (CR) injection-locked frequency divider (ILFD) for radar sensor applications is presented in this paper. A fourth-order resonator is designed using a transformer with a distributed inductor for wideband operating of the ILFD. The CR core is employed to reduce the power consumption compared to conventional cross-coupled pair ILFDs. The targeted input center frequency is 24 GHz for radar application. The self-oscillated frequency of the proposed CR-ILFD is 14.08 GHz. The input frequency locking range is from 18.8 to 33.8 GHz (57%) at an injection power of 0 dBm without a capacitor bank or varactors. The proposed CR-ILFD consumes 2.26 mW of power from a 1 V supply voltage. The entire die size is 0.75 mm × 0.45 mm. This CR-ILFD is implemented in a 65 nm complementary metal-oxide semiconductor (CMOS) technology.

Copper Ulsi Interconnect Technology

1998 ◽  
Vol 514 ◽  
Author(s):  
D. Edelstein
Keyword(s):  
High Performance ◽  
Stress Testing ◽  
Cmos Technology ◽  
Functional Verification ◽  
Functional Modules ◽  
Mos Devices ◽  
Potential Problems ◽  
Cu Contamination ◽  
Interconnect Technology ◽  
Better Than

ABSTRACTRecently IBM announced the first implementation of full copper ULSI wiring in a CMOS technology, to be manufactured on its high-performance 0.22 um CMOS products this year. Features of this technology will be presented, as well as functional verification on CMOS chips. To reach this level, extensive yield, reliability, and stress testing had to be done on test and product-like chips, including those packaged into product modules. Data will be presented fom all aspects of this testing, ranging from experiments designed to promote Cu contamination of the MOS devices, to temperature/humidity/bias stressing of assembled functional modules. The results in all areas are shown to be equal to or better than standards set by our current AI(Cu)/Wstud technology. This demonstrates that the potential problems associated with copper wiring that have long been discussed can be overcome.

scholarly journals A 2.4 GHz low noise amplifier design at 130nm CMOS technology using common gate topology for WiFi / WiMAX application

2017 ◽  
Vol 7 (1.3) ◽  
pp. 69
Author(s):  
M. Ramana Reddy ◽  
N.S Murthy Sharma ◽  
P. Chandra Sekhar
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Low Power Consumption ◽  
Common Gate ◽  
Chip Size ◽  
Overall Performance ◽  
Amplifier Design ◽  
Noise Amplifier

The proposed work shows an innovative designing in TSMC 130nm CMOS technology. A 2.4 GHz common gate topology low noise amplifier (LNA) using an active inductor to attain the low power consumption and to get the small chip size in layout design. By using this Common gate topology achieves the noise figure of 4dB, Forward gain (S21) parameter of 14.7dB, and the small chip size of 0.26 mm, while 0.8mW power consuming from a 1.1V in 130nm CMOS gives the better noise figure and improved the overall performance.

scholarly journals Design of area-efficient GHz range current mode frequency synthesizer using standard CMOS technology

2019 ◽  
Vol 70 (4) ◽  
pp. 323-328
Author(s):  
Dan-Dan Zheng ◽  
Yu-Bin Li ◽  
Chang-Qi Wang ◽  
Kai Huang ◽  
Xiao-Peng Yu
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Mode Frequency ◽  
Loop Filter ◽  
Silicon Area ◽  
Power Efficient ◽  
A Current

Abstract In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.

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