Metal and Polycrystalline Silicon Reactions

1989 ◽  
pp. 225-233 ◽  
Author(s):  
K. N. Tu ◽  
T. C. Chou
Keyword(s):  
Polycrystalline Silicon

Preparation of TEM samples by focused ion beams

1995 ◽  
Vol 53 ◽  
pp. 518-519
Author(s):  
John F. Walker ◽  
J C Reiner ◽  
C Solenthaler
Keyword(s):  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Field Effect Transistor ◽  
High Spatial Resolution ◽  
Ion Beam ◽  
Ion Beams ◽  
Focused Ion Beams ◽  
Precise Location ◽  
Effect Transistor ◽  
Circuit Technology

The high spatial resolution available from TEM can be used with great advantage in the field of microelectronics to identify problems associated with the continually shrinking geometries of integrated circuit technology. In many cases the location of the problem can be the most problematic element of sample preparation. Focused ion beams (FIB) have previously been used to prepare TEM specimens, but not including using the ion beam imaging capabilities to locate a buried feature of interest. Here we describe how a defect has been located using the ability of a FIB to both mill a section and to search for a defect whose precise location is unknown. The defect is known from electrical leakage measurements to be a break in the gate oxide of a field effect transistor. The gate is a square of polycrystalline silicon, approximately 1μm×1μm, on a silicon dioxide barrier which is about 17nm thick. The break in the oxide can occur anywhere within that square and is expected to be less than 100nm in diameter.

Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

1992 ◽  
Vol 50 (2) ◽  
pp. 1396-1397
Author(s):  
H. Yen ◽  
E. P. Kvam ◽  
R. Bashir ◽  
S. Venkatesan ◽  
G. W. Neudeck
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Interface Morphology ◽  
Oxide Interface ◽  
Poly Silicon ◽  
Thermal Oxide ◽  
Grain Orientations ◽  
Polycrystalline Silicon Films ◽  
P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

EVOLUTIONS OF GRAIN BOUNDARY RECOMBINATION ACTIVITY IN POLYCRYSTALLINE SILICON INVESTIGATED BY LBIC MAPPING AND DLTS

1989 ◽  
Vol 50 (C6) ◽  
pp. C6-160-C6-160
Author(s):  
M. PASQUINELLI ◽  
N. M'GAFFAD ◽  
H. AMANRICH ◽  
S. MARTINUZZI
Keyword(s):  
Grain Boundary ◽  
Polycrystalline Silicon ◽  
Recombination Activity

Effect of Thermal Annealing on Characteristics of Polycrystalline Silicon used for Solar Cells

2008 ◽  
Author(s):  
Gou XianFang ◽  
li xudong ◽  
xu ying ◽  
liang xinqing
Keyword(s):  
Solar Cells ◽  
Thermal Annealing ◽  
Polycrystalline Silicon
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