FPGA Design of MB-OFDM UWB Baseband System Based on Parallel Structure

Conventional distributed arithmetic (DA) is popular in field programmable gate array (FPGA) design, and it features on-chip ROM to achieve high speed and regularity. In this paper, we describe high speed area efficient 1-D discrete wavelet transform (DWT) using 9/7 filter based new efficient distributed arithmetic (NEDA) Technique. Being area efficient architecture free of ROM, multiplication, and subtraction, NEDA can also expose the redundancy existing in the adder array consisting of entries of 0 and 1. This architecture supports any size of image pixel value and any level of decomposition. The parallel structure has 100% hardware utilization efficiency.

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Embedded FPGA Design for Optimal Pixel Adjustment Process of Image Steganography

Mathematical Problems in Engineering ◽

10.1155/2018/5216029 ◽

2018 ◽

Vol 2018 ◽

pp. 1-8

Author(s):

Chiung-Wei Huang ◽

Changmin Chou ◽

Yu-Che Chiu ◽

Cheng-Yuan Chang

Keyword(s):

Image Steganography ◽

Cover Image ◽

Parallel Structure ◽

Secret Message ◽

Adjustment Process ◽

Fpga Design ◽

Stego Image ◽

Field Programmable ◽

Speed Up ◽

Hardware Processing

We propose a prototype of field programmable gate array (FPGA) implementation for optimal pixel adjustment process (OPAP) algorithm of image steganography. In the proposed scheme, the cover image and the secret message are transmitted from a personal computer (PC) to an FPGA board using RS232 interface for hardware processing. We firstly embed k-bit secret message into each pixel of the cover image by the last-significant-bit (LSB) substitution method, followed by executing associated OPAP calculations to construct a stego pixel. After all pixels of the cover image have been embedded, a stego image is created and transmitted from FPGA back to the PC and stored in the PC. Moreover, we have extended the basic pixel-wise structure to a parallel structure which can fully use the hardware devices to speed up the embedding process and embed several bits of secret message at the same time. Through parallel mechanism of the hardware based design, the data hiding process can be completed in few clock cycles to produce steganography outcome. Experimental results show the effectiveness and correctness of the proposed scheme.

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Implementation and Application of Short-Time Fourier Transform on a New High Speed FPGA

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.556-562.1838 ◽

2014 ◽

Vol 556-562 ◽

pp. 1838-1841

Author(s):

Gui Gui ◽

Li Peng Qiu

Keyword(s):

Fourier Transform ◽

High Speed ◽

Parallel Structure ◽

Short Time Fourier Transform ◽

Fpga Design ◽

Work Condition ◽

Time Frequency ◽

Actual Signal ◽

Pipe Line ◽

Short Time

FPGA structures are common designed in Serial structure and Parallel structure. As the most efficient one, Parallel structure also could be divided into whole-parallel and half-parallel which we called pipe-line structure. Whole Parallel structure FPGA take a great advantage on speed but consuming enormous resources. Moreover, FFT cannot give enough details on Time-frequency domain. In order to avoid these disadvantages, proposed STFT processer plan on FPGA. Based on the research on algorithms STFT, we gave an improved pipeline structure FPGA design. Then this design implied high speed STFT which take both speed and precision into count on FPGA. At the last of this paper, we conducted signal test. In this step , any signals were all collected from actual work condition. And then verify the feasibility of the program through simulation and actual signal test.

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Increasing the information capacity of a fiber-optic multi-sensor converter of binary mechanical signals into electrical signals

Izmeritel`naya Tekhnika ◽

10.32446/0368-1025it.2020-9-15-23 ◽

2020 ◽

pp. 15-23

Author(s):

V. M. Grechishnikov ◽

E. G. Komarov

Keyword(s):

Fiber Optic ◽

Information Capacity ◽

Parallel Structure ◽

Optical Scheme ◽

Digital To Analog Converter ◽

Electrical Signals ◽

Mechanical Signals ◽

Analog Converter ◽

Output Code ◽

Digital To Analog

The design and operation principle of a multi-sensor Converter of binary mechanical signals into electrical signals based on a partitioned fiber-optic digital-to-analog Converter with a parallel structure is considered. The digital-to-analog Converter is made from a set of simple and technological (three to five digit) fiber-optic digital-to-analog sections. The advantages of the optical scheme of the proposed. Converter in terms of metrological and energy characteristics in comparison with single multi-bit converters are justified. It is shown that by increasing the number of digital-analog sections, it is possible to repeatedly increase the information capacity of a multi-sensor Converter without tightening the requirements for its manufacturing technology and element base. A mathematical model of the proposed Converter is developed that reflects the features of its operation in the mode of sequential time conversion of the input code vectors of individual fiber-optic sections into electrical analogues and the formation of the resulting output code vector.

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Overview on FPGA Design Implementations for Autonomous Cars

10.33107/ubt-ic.2018.100 ◽

2018 ◽

Author(s):

Galia Marinova

Keyword(s):

Fpga Design ◽

Autonomous Cars

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Parallel and sequential structures of manipulators in robotic surgery

Доклады Академии наук ◽

10.31857/s0869-56524852166-170 ◽

2019 ◽

Vol 485 (2) ◽

pp. 166-170

Author(s):

E. I. Veliev ◽

R. F. Ganiev ◽

V. A. Glazunov ◽

G. S. Filippov

Keyword(s):

Robotic Surgery ◽

Robotic System ◽

Parallel Structure ◽

Manipulation System ◽

Surgical Manipulation ◽

Surgical Operations

The problems of modern robotics associated with the requirements for devices designed for various purposes are considered. The daVinci robotic surgical manipulation system is analyzed. The developed robotic system with a parallel structure designed for various kinds of surgical operations is proposed.

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