Noise Voltage: A New Dependability Concern in Low-Power FinFET-Based Priority Encoder at 45 nm Technology

2020 ◽  
pp. 411-418
Author(s):  
Vishwas Mishra ◽  
Abhishek Kumar ◽  
Shobhit Tyagi ◽  
Divya Mishra ◽  
Shyam Akashe
Keyword(s):  
Low Power ◽  
Noise Voltage ◽  
Priority Encoder

AN ULTRA-LOW-POWER CURRENT-MODE INTEGRATED CMOS INSTRUMENTATION AMPLIFIER FOR PERSONAL ECG RECORDERS

2008 ◽  
Vol 17 (06) ◽  
pp. 1053-1067 ◽  
Author(s):  
MARYAM SHOJAEI BAGHINI ◽  
SUDIP NAG ◽  
RAKESH K. LAL ◽  
DINESH K. SHARMA
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Current Mode ◽  
Corner Frequency ◽  
Noise Voltage ◽  
Instrumentation Amplifier ◽  
Ecg Signal ◽  
Signal Conditioning ◽  
Ultra Low Power ◽  
Measurement Results

This paper presents an ultra-low-power current-mode ECG instrumentation amplifier, which is designed based on the current balancing technique and fabricated in TSMC 0.35 μm CMOS process. The instrumentation amplifier, which is presented here has three features. First, the instrumentation amplifier is a full-CMOS implementation of current-balancing technique applied for ECG signal conditioning. Second, the instrumentation amplifier is of ultra-low-power due to a power-oriented design methodology, which makes its power consumption very low compared to the earlier reported works for ECG recording applications. Third, integrated programmable bandpass filtering is implemented in the amplifier itself, which provides a compact solution for analog ECG signal conditioning. Measurement results show that the amplifier only draws 9 μA current from a 3.3 V lithium-ion battery, while CMRR of 100 dB and input voltage dynamic range of ± 6 mV are achieved. By considering trade-offs between input noise voltage and power, noise performance was compromised with power and area for ultra-low-power ECG signal conditioning applications. Measurement results show [Formula: see text] input referred noise voltage with a flicker noise corner frequency of 15 Hz at 9 μA dc current and small area, which is appropriate for the desired application. Measurement results meet the recommended specifications for signal conditioning of portable ECG monitoring devices. Design methodology, fabrication considerations, measurement setup, and experimental results are also explained in this paper.

scholarly journals A Low Power Flash ADC using Single-Electron Transistor

2019 ◽  
Vol 8 (9) ◽  
pp. 568-572
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Single Electron ◽  
Single Electron Transistor ◽  
Ultra Low Power ◽  
Flash Adc ◽  
Terminal Set ◽  
Small Quantum ◽  
Voltage Swing ◽  
Priority Encoder

This paper proposes an analog-digital converter (ADC) using Single-electron transistor (SET).Single Electron Transistor is Nanodevice having a small quantum dot or island instead of the channel that works on the principle of Coulomb blockadewhich allows one electron tunnelingat a time from source to drain terminal. SET operates at low voltage and consumes lesspower. The proposed Flash ADC consists of SET based priority encoder and comparator circuits. The proposed design offers large input/output voltage swing, ultra-low power, compact circuit block for ADC compared to SET/CMOS hybrid amplifier-based ADC. In this paper, we have designed a 4-bit and 8bitFlash ADC using SET operating at room temperature and the performance estimationwas performed by using the CADENCE VIRTUOSO simulator

scholarly journals A Novel low power 2-D to 3-D Array Priority Encoder using Split-Logic Technique for Data Path Applications

2022 ◽  
Vol 17 ◽  
pp. 42-49
Author(s):  
D. S. Shylu Sam ◽  
P. Sam Paul ◽  
Jennifer , Elizah ◽  
Nithyasri Nithyasri ◽  
Snehitha Snehitha ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Matrix Form ◽  
Data Path ◽  
Input File ◽  
Synthesis Tool ◽  
The Matrix ◽  
Simulation Results ◽  
A Priority ◽  
Priority Encoder

In this work, an ascendable low power 64-bit priority encoder is designed using a two-directional array to three-directional array conversion, and Split-logic technique and 6-bit is obtained as the output. By using this method, the high performance priority encoder can be achieved. In the conventional priority encoder, a single bit is set as an input, but for a priority encoder with 3-Darray, every input are specified in the matrix form. The I-bit input file is split hooked on M × N bits, similar to 2-D Matrix. In priority encoder with 3-Darray, three directional output comes out, unlike traditional priority encoder, where the output is received from one direction. The development can be achieved by implementing the two-directional array to three-directional array technique. Simulation results show that the proposed 2-D and 3-D priority encoder consumes 0.087039mW and 0.184014mW which is less when compared with the conventional priority encoder. The priority encoders are simulated and synthesized using VHDL in Xilinx Vivado version 2019.2 and the Oasys synthesis tool.

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