scholarly journals A Novel low power 2-D to 3-D Array Priority Encoder using Split-Logic Technique for Data Path Applications

2022 ◽  
Vol 17 ◽  
pp. 42-49
Author(s):  
D. S. Shylu Sam ◽  
P. Sam Paul ◽  
Jennifer , Elizah ◽  
Nithyasri Nithyasri ◽  
Snehitha Snehitha ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Matrix Form ◽  
Data Path ◽  
Input File ◽  
Synthesis Tool ◽  
The Matrix ◽  
Simulation Results ◽  
A Priority ◽  
Priority Encoder

In this work, an ascendable low power 64-bit priority encoder is designed using a two-directional array to three-directional array conversion, and Split-logic technique and 6-bit is obtained as the output. By using this method, the high performance priority encoder can be achieved. In the conventional priority encoder, a single bit is set as an input, but for a priority encoder with 3-Darray, every input are specified in the matrix form. The I-bit input file is split hooked on M × N bits, similar to 2-D Matrix. In priority encoder with 3-Darray, three directional output comes out, unlike traditional priority encoder, where the output is received from one direction. The development can be achieved by implementing the two-directional array to three-directional array technique. Simulation results show that the proposed 2-D and 3-D priority encoder consumes 0.087039mW and 0.184014mW which is less when compared with the conventional priority encoder. The priority encoders are simulated and synthesized using VHDL in Xilinx Vivado version 2019.2 and the Oasys synthesis tool.

Steep-Slope Devices: Prospects and Challenges

2016 ◽  
Vol 39 ◽  
pp. 3-16 ◽  
Author(s):  
Elena Gnani ◽  
Emanuele Baravelli ◽  
Pasquale Maiorano ◽  
Antonio Gnudi ◽  
Susanna Reggiani ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Supply Voltage ◽  
Steep Slope ◽  
Oxide Interface ◽  
Novel Device ◽  
Tunnel Fet ◽  
Standby Power ◽  
Simulation Results ◽  
Low Performance

In this work, an overview is given on the prospects and challenges of two novel device concepts,namely the Tunnel FET (TFET) and the Superlattice FET (SL-FET). The optimization effort ofhomo- and hetero-junction TFETs carried out so far shows that these devices can provide an advantageover CMOS FETs only for very-low power and low-performance niche applications, so long asthe supply voltage is scaled below 300 mV. The required materials for homojunction TFETs are lowbandgap semiconductors, such as InAs and InGaAs; for heterojunction TFETs the best semiconductorpair appears to be (Al)GaSb-InAs. Several technological problems are still unsolved: poor qualityof the oxide interface with III-V materials and device variability are probably the most important. The SL-FET represents in principle a better device concept, as it provides outstanding performance and meets nearly all targets of the high performance (HP), low operating power (LOP) and low standby power (LSTP) of the ITRS at VDD = 0.4V. A suitably-designedInGaAs-InAlAs SL-FET has turned out to provide the best simulation results. However, the fabricationprocess of SL-FETs is much more complex, as it requires molecular epitaxy to deposit multiplelayers with a very strict control of their nanometric thickness. Besides, vertical devices can poseunexpected problems as far as layout organization and parasitics are concerned.

scholarly journals Designing a Novel High Performance Four-to-Two Compressor Cell Based on CNTFET Technology for Low Voltages

2018 ◽  
Vol 8 (6) ◽  
pp. 4863
Author(s):  
Mehdi Bagherizadeh ◽  
Mona Moradi ◽  
Mostafa Torabi
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
Critical Path ◽  
Low Power Design ◽  
Software Simulation ◽  
Majority Function ◽  
Simulation Results

<p>Compressor cell is often placed in critical path of multiplier circuits to perform partial product summation. Therefore it plays a significant role in determining the entire performance of multiplier and digital system. Respecting to the necessity of low power design for portable electronic, designing a low power and high performance compressors seems to be a good solution to overcome of these problems for computations. In this paper a novel high performance four-to-two compressor cell is proposed using Carbon Nanotube Field Effect Transistors (CNTFETs) technology. The new cell is based on Majority Function, NOR, and NAND gates. The main advantage of proposed design in comparison with former cells is the ease of obtaining CARRY output by means of Majority function. Simulations have been done with 32nm technology node using Synopsys HSPICE software. Simulation results confirm the priority of the proposed cell compared to other state-of-the-art four-to-two compressor cells.</p>

scholarly journals CORDIC Hardware Acceleration Using DMA-Based ISA Extension

2022 ◽  
Vol 12 (1) ◽  
pp. 4
Author(s):  
Erez Manor ◽  
Avrech Ben-David ◽  
Shlomo Greenberg
Keyword(s):  
Low Power ◽  
High Performance ◽  
Low Cost ◽  
Hardware Acceleration ◽  
Embedded Processors ◽  
Data Path ◽  
Instruction Set ◽  
Mathematical Functions ◽  
Coordinate Rotation ◽  
Software Implementations

The use of RISC-based embedded processors aimed at low cost and low power is becoming an increasingly popular ecosystem for both hardware and software development. High-performance yet low-power embedded processors may be attained via the use of hardware acceleration and Instruction Set Architecture (ISA) extension. Recent publications of AI have demonstrated the use of Coordinate Rotation Digital Computer (CORDIC) as a dedicated low-power solution for solving nonlinear equations applied to Neural Networks (NN). This paper proposes ISA extension to support floating-point CORDIC, providing efficient hardware acceleration for mathematical functions. A new DMA-based ISA extension approach integrated with a pipeline CORDIC accelerator is proposed. The CORDIC ISA extension is directly interfaced with a standard processor data path, allowing efficient implementation of new trigonometric ALU-based custom instructions. The proposed DMA-based CORDIC accelerator can also be used to perform repeated array calculations, offering a significant speedup over software implementations. The proposed accelerator is evaluated on Intel Cyclone-IV FPGA as an extension to Nios processor. Experimental results show a significant speedup of over three orders of magnitude compared with software implementation, while applied to trigonometric arrays, and outperforms the existing commercial CORDIC hardware accelerator.

scholarly journals A 6-bit Low-Power High-Speed Flash ADC using 180 nm CMOS process

2014 ◽  
Vol 17 (1) ◽  
pp. 52-61
Author(s):  
Thanh Tri Vo ◽  
Trong Tu Bui ◽  
Duc Hung Le ◽  
Cong Kha Pham
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Sampling Rate ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Flash Adc ◽  
High Sampling Rate ◽  
Simulation Results

In this paper we present a design of Flash-ADC that can achieve high performance and low power consumption. By using the Double Sampling Rate technique and a new comparator topology with low kick-back noise, this design can achieve high sampling rate while still consuming low power. The design is implemented in a 0.18 m CMOS process. The simulation results show that this design can work at 400 MSps and power consumption is only 16.24 mW. The DNL and INL are 0.15 LSB and 0.6 LSB, respectively.

Morphology of High-Performance Rigid-Rod Polymer Fibers and Molecular Composites

1989 ◽  
Vol 47 ◽  
pp. 338-339
Author(s):  
W.W. Adams ◽  
S. J. Krause
Keyword(s):  
Tensile Strength ◽  
High Performance ◽  
Liquid Crystalline ◽  
Molecular Level ◽  
Synergistic Effects ◽  
Tensile Modulus ◽  
Commercial Development ◽  
The Matrix ◽  
Molecular Composites ◽  
Rigid Rod

Rigid-rod polymers such as PBO, poly(paraphenylene benzobisoxazole), Figure 1a, are now in commercial development for use as high-performance fibers and for reinforcement at the molecular level in molecular composites. Spinning of liquid crystalline polyphosphoric acid solutions of PBO, followed by washing, drying, and tension heat treatment produces fibers which have the following properties: density of 1.59 g/cm3; tensile strength of 820 kpsi; tensile modulus of 52 Mpsi; compressive strength of 50 kpsi; they are electrically insulating; they do not absorb moisture; and they are insensitive to radiation, including ultraviolet. Since the chain modulus of PBO is estimated to be 730 GPa, the high stiffness also affords the opportunity to reinforce a flexible coil polymer at the molecular level, in analogy to a chopped fiber reinforced composite. The objectives of the molecular composite concept are to eliminate the thermal expansion coefficient mismatch between the fiber and the matrix, as occurs in conventional composites, to eliminate the interface between the fiber and the matrix, and, hopefully, to obtain synergistic effects from the exceptional stiffness of the rigid-rod molecule. These expectations have been confirmed in the case of blending rigid-rod PBZT, poly(paraphenylene benzobisthiazole), Figure 1b, with stiff-chain ABPBI, poly 2,5(6) benzimidazole, Fig. 1c A film with 30% PBZT/70% ABPBI had tensile strength 190 kpsi and tensile modulus of 13 Mpsi when solution spun from a 3% methane sulfonic acid solution into a film. The modulus, as predicted by rule of mixtures, for a film with this composition and with planar isotropic orientation, should be 16 Mpsi. The experimental value is 80% of the theoretical value indicating that the concept of a molecular composite is valid.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

Sign in / Sign up

Export Citation Format

Share Document