High-Performance Digital Logic Circuit Realization Using Differential Cascode Voltage Switch Logic (DCVSL)

2020 ◽  
pp. 161-170
Author(s):  
S. S. Kavitha ◽  
Narasimha Kaulgud
Keyword(s):  
High Performance ◽  
Logic Circuit ◽  
Digital Logic ◽  
Circuit Realization

Conversion Method of Description Files in Structural Testing of Digital Circuit

2013 ◽  
Vol 427-429 ◽  
pp. 1285-1288
Author(s):  
Kang Yi Wang
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Digital Circuit ◽  
Logic Circuit ◽  
Structural Testing ◽  
Digital Logic ◽  
Continuous Development ◽  
Program Correctness ◽  
Testing Program ◽  
Circuit Technology

With the continuous development of large-scale integrated circuit technology, the importance of structural testing and testability design for digital logic circuit has become increasingly evident. In the testing domain, Bench is the most commonly used formats to describe a measured circuit. In order to test the measured circuit using computer, files with various formats must be converted to a netlist file which can be identified by computer. Lev format is a common netlist file. This paper mainly discusses how to convert the Bench file into Lev file, and it is proved by testing program correctness and robustness.

Development of a set of mutually compatible digital logic circuit modules

1969 ◽  
Vol 7 (1) ◽  
pp. 7 ◽  
Author(s):  
R. Srinivasan ◽  
K.R. Srinivasan
Keyword(s):  
Logic Circuit ◽  
Digital Logic

High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit

2021 ◽  
Author(s):  
Dong Han Ko ◽  
Sehee Lim ◽  
Young Kyu Lee ◽  
Seong-Ook Jung
Keyword(s):  
High Performance ◽  
Logic Circuit ◽  
Reconfigurable Logic ◽  
Area Efficient

Novel digital logic gate for high-performance CMOS imaging system

2004 ◽  
Author(s):  
Hoon H. Chung ◽  
Youngjoong Joo
Keyword(s):  
High Performance ◽  
Imaging System ◽  
Logic Gate ◽  
Digital Logic

Novel vs Conventional Bipolar Logic Circuit Topologies in 4H-SiC

2016 ◽  
Vol 858 ◽  
pp. 1103-1106 ◽  
Author(s):  
Hazem Elgabra ◽  
Amna Siddiqui ◽  
Shakti Singh
Keyword(s):  
Silicon Carbide ◽  
Electrical Properties ◽  
Integrated Circuits ◽  
Logic Circuit ◽  
Digital Logic ◽  
Harsh Environment ◽  
The Novel ◽  
Attractive Candidate ◽  
Silicon Based

Silicon Carbide (SiC) is an attractive candidate for integrated circuits (ICs) in harsh environment applications due to its superior inherent electrical properties. Though current research is geared towards adapting existing silicon based digital logic technologies to 4H-SiC, the true merit of each technology in 4H-SiC has remained unclear. Creating logic technologies specifically for 4H-SiC, taking into account its electrical properties, is an area which remains unexplored. In this paper, we present a novel bipolar logic technology that is designed and optimized for 4H-SiC, and compare its performance with the prevalent bipolar technologies. The results show that the novel logic technology not only compares well with the conventional technologies in performance, but also features simpler design, smaller footprint, and a low transistor count.

scholarly journals Effectiveness of Blended Learning Method on Digital Logic Circuit

2015 ◽  
Vol 4 (2) ◽  
pp. 34-37
Author(s):  
Se-Young Lim ◽  
Dong-Kyun Lim ◽  
Ji-Eun Lee
Keyword(s):  
Blended Learning ◽  
Logic Circuit ◽  
Digital Logic ◽  
Learning Method

Low Power Structural Design of 2–4 and 4–16 Line Decoder Logic Circuit

2020 ◽  
Vol 17 (5) ◽  
pp. 2266-2272
Author(s):  
Nikita Kar Chowdhury ◽  
R. Dhanabal ◽  
V. N. Ramakrishnan
Keyword(s):  
Low Power ◽  
Structural Design ◽  
Logic Circuit ◽  
Digital Logic ◽  
Transmission Gate

An analysis of low power 2–4 decoder and 4–16 decoders are made and comparing it with the proposed decoders. The decoder logic circuit have been made utilizing Dual Value Logic (DVL) and Transmission gate logic to actualize a fourteen transistors 2–4 decoder for limiting the transistor count. By utilizing 2–4 pre-decoders and post-decoders to execute 4–16 decoder. Blended digital logic is additionally utilized for this reason. In correlation we have execute a solitary 2–4 decoder with least transistor check and low power utilization which is utilized to structure a 4–16 decoder. CADENCE Virtuoso simulation at 90 nm technology is used and calculated the power and area. We thus made a tabular comparison of our results with the results from previous researches.

scholarly journals Design of High-performance Digital Logic Circuits based on FinFET Technology

2012 ◽  
Vol 41 (20) ◽  
pp. 40-44 ◽  
Author(s):  
V Narendar ◽  
Wanjul Dattatray R ◽  
Sanjeev Rai ◽  
R. A. Mishra
Keyword(s):  
High Performance ◽  
Logic Circuits ◽  
Digital Logic
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