Design and Implementation of Power-Efficient and Fast Full Adders Using Hybrid Logics

Mapping Intimacies ◽

10.1007/978-981-16-1342-5_9 ◽

2021 ◽

pp. 119-133

Author(s):

Chilukuri Sai Vamsi ◽

Sanagaram Aravind Kasyap ◽

S. Saiprateeka ◽

Sonali Agrawal

Keyword(s):

Power Efficient ◽

Design And Implementation

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Design and Implementation of Area-Power Efficient Generic Modular Adder using Flagged Prefix Addition Approach

10.1109/icsc53193.2021.9673363 ◽

2021 ◽

Author(s):

Tukur Gupta ◽

Shamim Akhter

Keyword(s):

Power Efficient ◽

Design And Implementation

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The Design and Implementation of a Power Efficient Embedded SRAM

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/978-3-540-74442-9_9 ◽

2007 ◽

pp. 86-96

Author(s):

Yijun Liu ◽

Pinghua Chen ◽

Wenyan Wang ◽

Zhenkun Li

Keyword(s):

Power Efficient ◽

Design And Implementation ◽

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Design and Implementation of Power Efficient Logic BIST With High Fault Coverage Using Verilog

2018 International Conference on Networking, Embedded and Wireless Systems (ICNEWS) ◽

10.1109/icnews.2018.8903923 ◽

2018 ◽

Author(s):

K Akhila ◽

N Karuna ◽

Yasha Jyothi M Shirur

Keyword(s):

Fault Coverage ◽

Power Efficient ◽

Design And Implementation ◽

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A Power Efficient Binary Multiplier Circuit with Overflow Detection Using Single Spin Logic Circuit: Design and Implementation

Advanced Science Letters ◽

10.1166/asl.2009.1071 ◽

2009 ◽

Vol 2 (3) ◽

pp. 391-397

Author(s):

Ankush Ghosh ◽

Souvik Sarkar ◽

D. Ray Chaudhuri ◽

Subir Kumar Sarkar

Keyword(s):

Circuit Design ◽

Logic Circuit ◽

Power Efficient ◽

Single Spin ◽

Design And Implementation ◽

Binary Multiplier ◽

Multiplier Circuit

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Design and implementation of area-delay-power efficient CSLA based 32-bit array multiplier

2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) ◽

10.1109/rteict.2017.8256864 ◽

2017 ◽

Author(s):

N. Fahmina Afreen ◽

M. Mahaboob Basha ◽

S. Mohan Das

Keyword(s):

Power Efficient ◽

Design And Implementation ◽

Array Multiplier

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A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

Integration ◽

10.1016/j.vlsi.2019.02.008 ◽

2019 ◽

Vol 66 ◽

pp. 164-172

Author(s):

Xing Wei ◽

Haigang Yang ◽

Wei Li ◽

Zhihong Huang ◽

Tao Yin ◽

...

Keyword(s):

Binary Tree ◽

Tree Decomposition ◽

Floating Point ◽

Processor Design ◽

Power Efficient ◽

Design And Implementation ◽

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Power Efficient Gurumukhi Unicode Reader Design and Implementation on FPGA

International Journal of New Computer Architectures and their Applications ◽

10.17781/p002436 ◽

2018 ◽

Vol 8 (2) ◽

pp. 83-88

Author(s):

D M Akbar Hussain ◽

Keyword(s):

Power Efficient ◽

Design And Implementation

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Design and Implementation of Power Efficient Modified Russian Peasant Multiplier using Ripple Carry Adder

International Journal of MC Square Scientific Research ◽

10.20894/ijmsr.117.009.002.018 ◽

2017 ◽

Vol 9 (2) ◽

pp. 154-165

Author(s):

N.C. sendhilkumar ◽

Keyword(s):

Power Efficient ◽

Design And Implementation ◽

Ripple Carry Adder

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Design and Implementation of an Area and Power Efficient Switched-Capacitor Based Embedded DC–DC Converter

Journal of Low Power Electronics ◽

10.1166/jolpe.2012.1185 ◽

2012 ◽

Vol 8 (2) ◽

pp. 207-222

Author(s):

Biswajit Maity ◽

Soumya Gangula ◽

Pradip Mandal

Keyword(s):

Switched Capacitor ◽

Power Efficient ◽

Design And Implementation

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Design and Implementation of Power Efficient Micro Pipelined GALS Based 2-D FFT Processor Core

International Journal of Signal Processing Systems ◽

10.12720/ijsps.3.2.166-171 ◽

2014 ◽

Vol 3 (2) ◽

Author(s):

Y. J. M. Shirur ◽

V. S. Chakravarthi

Keyword(s):

Power Efficient ◽

Processor Core ◽

Design And Implementation ◽

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