In modern days of VLSI design, speedy operations and low-power consumption is a key requirement for any circuits. When it comes to multipliers, the power efficient multiplier plays an important role. The main aim of this work is to develop the system with faster and less power multiplier
for an efficient process by using Baugh-Wooley multipliers. The optimized Baugh-Wooley multiplier consumes least power, area and produces less delay. The proposed architecture is 193× times faster than Conventional array multiplier in the practical applications and 213× times faster
than a conventional Baugh-Wooley multiplier. The Improved Baugh-Wooley multiplier consumes the power of 09.02 mW and area of 52426 μm2.
Design and Implementation of 3*3 Array Multiplier using DPTL Logic