Energy Efficient Error Resilient Multiplier Using Low-power Compressors

2022 ◽  
Vol 27 (3) ◽  
pp. 1-26
Author(s):  
Skandha Deepsita S ◽  
Dhayala Kumar M ◽  
Noor Mahammad SK
Keyword(s):  
Low Power ◽  
High Speed ◽  
Energy Savings ◽  
Approximate Algorithm ◽  
Image Processing Algorithm ◽  
Acceptable Error ◽  
High Speed Design ◽  
The Cost ◽  
Error Profiles ◽  
Error Distance

The approximate hardware design can save huge energy at the cost of errors incurred in the design. This article proposes the approximate algorithm for low-power compressors, utilized to build approximate multiplier with low energy and acceptable error profiles. This article presents two design approaches (DA1 and DA2) for higher bit size approximate multipliers. The proposed multiplier of DA1 have no propagation of carry signal from LSB to MSB, resulted in a very high-speed design. The increment in delay, power, and energy are not exponential with increment of multiplier size ( n ) for DA1 multiplier. It can be observed that the maximum combinations lie in the threshold Error Distance of 5% of the maximum value possible for any particular multiplier of size n . The proposed 4-bit DA1 multiplier consumes only 1.3 fJ of energy, which is 87.9%, 78%, 94%, 67.5%, and 58.9% less when compared to M1, M2, LxA, MxA, accurate designs respectively. The DA2 approach is recursive method, i.e., n -bit multiplier built with n/2-bit sub-multipliers. The proposed 8-bit multiplication has 92% energy savings with Mean Relative Error Distance (MRED) of 0.3 for the DA1 approach and at least 11% to 40% of energy savings with MRED of 0.08 for the DA2 approach. The proposed multipliers are employed in the image processing algorithm of DCT, and the quality is evaluated. The standard PSNR metric is 55 dB for less approximation and 35 dB for maximum approximation.

scholarly journals Low Power/ High Speed Design in VLSI with the application of Pipelining and Parallel processing

2012 ◽  
Vol 2 (3) ◽  
pp. 96-101
Author(s):  
Shilpa Sathish ◽  
C. Lakshminarayana
Keyword(s):  
Parallel Processing ◽  
Low Power ◽  
High Speed ◽  
Vlsi Design ◽  
Percentage Reduction ◽  
High Speed Design

The main objectives of any VLSI design are Power, Delay andArea. Minimizing all the objectives is a challenge in presentsituation but all efforts to achieve one of these can lead to abetter design. This paper proposes an EDA tool for low power/high speed VLSI design, which solves any DFG to estimate thespeed of operation and the percentage reduction in the powerconsumption using pipelining and parallel processing concepts

Novel 4:2 Approximate Compressor Designs for Multimedia and Neural Network Applications

2020 ◽  
pp. 2150138
Author(s):  
Pranose J. Edavoor ◽  
Sithara Raveendran ◽  
Amol D. Rahulkar
Keyword(s):  
Neural Network ◽  
Low Power ◽  
High Speed ◽  
Signal To Noise Ratio ◽  
Structural Similarity ◽  
Recognition System ◽  
Network Applications ◽  
Average Accuracy ◽  
Low Power Dissipation ◽  
Error Distance

Low power dissipation in approximate arithmetic circuits has laid the foundation for area-efficient computational units for error resilient applications like image and signal processing. This paper proposes two novel low power high speed architectures for approximate 4:2 compressor that can be employed in multipliers for partial product summation. The two designs presented ([Formula: see text] and [Formula: see text]) have Error Distance (ED) of [Formula: see text] and Error Rate (ER) of 25%. The proposed [Formula: see text] and [Formula: see text] are able to achieve reduction in power and delay by (62.50%, 47.67%) and (83.13%, 60.20%), respectively, in comparison with the exact 4:2 compressor. To verify the effectiveness of the design, the proposed architectures are used to implement [Formula: see text] Dadda multiplier. The equal number of errors in positive and negative directions in the proposed designs aid in reducing the Mean Error Distance (MED) and Mean Relative Error Distance (MRED) of the multiplier. Multiplication of images and two-level decomposition of 2D Haar wavelets are implemented using the designed Dadda multiplier. The efficiency of the image processing applications is measured in terms of Mean Structural Similarity (MSSIM) index and Peak Signal-to-Noise Ratio (PSNR) and an average of 0.98 and 35[Formula: see text]dB, respectively, is obtained, which are in the acceptable range. In addition, a Convolutional Neural Network (CNN)-based LeNet-1 Handwritten Digit Recognition System (HDRS) is implemented using the proposed compressor-based multipliers. The proposed compressor-based architectures are able to achieve an average accuracy of 96.23%.

Low-power and high-speed design of a versatile bit-serial multiplier in finite fields GF(2 )

Integration ◽  
2013 ◽  
Vol 46 (2) ◽  
pp. 211-217 ◽  
Author(s):  
Ali Zakerolhosseini ◽  
Morteza Nikooghadam
Keyword(s):  
Low Power ◽  
Finite Fields ◽  
High Speed ◽  
High Speed Design ◽  
Bit Serial

scholarly journals A Systematic Assessment of W-Doped CoFeB Single Free Layers for Low Power STT-MRAM Applications

Electronics ◽  
2021 ◽  
Vol 10 (19) ◽  
pp. 2384
Author(s):  
Siddharth Rao ◽  
Sebastien Couet ◽  
Simon Van Beek ◽  
Shreya Kundu ◽  
Shamin Houshmand Sharifi ◽  
...  
Keyword(s):  
Low Power ◽  
Nonvolatile Memory ◽  
High Speed ◽  
Random Access ◽  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Systematic Assessment ◽  
Current Reduction ◽  
The Cost ◽  
Alternative Designs

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) technology is considered to be the most promising nonvolatile memory (NVM) solution for high-speed and low power applications. Dual MgO-based composite free layers (FL) have driven the development of STT-MRAMs over the past decade, achieving data retention of 10 years at the cost of higher write power consumption. In addition, the need for tunnel magnetoresistance (TMR)-based read schemes limits the flexibility in materials beyond the typical CoFeB/MgO interfaces. In this study, we propose a novel spacerless FL stack comprised of CoFeB alloyed with heavy metals such as tungsten (W) which allows effective modulation of the magnet properties (Ms, Hk) while retaining compatibility with MgO layers. The addition of W results favours a delayed crystallization process, in turn enabling higher thermal budgets up to 180 min at 400 °C. The presence of tungsten reduces the total FL magnetization (Ms) but simultaneously increasing its temperature dependence, thus, enabling a dynamic write current reduction of ~15% at 2 ns pulse widths. Reliable operation is demonstrated with a WER of 1 ppm and endurance >1010 cycles. These results pave the way for alternative designs of STT-MRAMs for low power electronics.

scholarly journals Noise measurement in high-speed domino pseudo-CMOS keeper

2018 ◽  
Vol 52 (1-2) ◽  
pp. 20-27
Author(s):  
R Jaikumar ◽  
P Poongodi
Keyword(s):  
Low Power ◽  
High Speed ◽  
Noise Immunity ◽  
Delay Reduction ◽  
Power Dynamic ◽  
Unity Noise Gain ◽  
Power Delay Product ◽  
The Cost ◽  
Domino Circuits ◽  
Or Gate

Noise immunity is the foremost issue in high-speed domino circuits. In general, better noise immunity is achieved at the cost of speed and power degradation. In this paper, pseudo-dynamic keeper design is proposed to reduce the delay and power with improved noise immunity for domino circuits. The proposed technique is able to achieve reduced delay, power consumption, and better noise immunity by using always ON keeper. The simulation results show that the proposed technique exhibits 41%, 39%, and 19% delay reduction when compared with the low power dynamic circuit for two-input OR gate, two-input EX-OR gate, and 4:1 multiplexer. The proposed logic also performs better as compared to a low power dynamic circuit with 24%, 21%, and 14% reduction in power-delay product for two-input OR gate, two-input EX-OR gate, and four input MUX, respectively. The unity noise gain is also improved as compared to all other existing methods.

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