Design of a wideband low-power continuous-time ΣΔ modulator in 90 nm CMOS technology

A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one of the most widely adopted OTAs for neural recording amplifiers. The proposed CMFB also consumes no additional power, i.e., no separate CMFB amplifier is required, thus, it fits well to low-power, area-constrained multichannel neural recording amplifiers. The proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional differential difference amplifier-based CMFB in 0.18 μm CMOS technology post-layout simulations. The AC-coupled neural recording amplifier with the proposed CMFB occupies ~37% less area and consumes ~11% smaller power, providing 2.67× larger output common mode (CM) range without CM bandwidth sacrifice in the comparison.

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Design of an Ultra-Low Power CT ΣΔ A/D Modulator in 65 nm CMOS for Cardiac Pacemakers: From System Synthesis to Circuit Implementation

International Journal of Electronics and Telecommunications ◽

10.2478/eletel-2014-0013 ◽

2014 ◽

Vol 60 (1) ◽

pp. 98-104 ◽

Cited By ~ 1

Author(s):

Yelin Wang ◽

Hao Cai

Keyword(s):

Low Power ◽

Continuous Time ◽

Cardiac Pacemaker ◽

Design Procedure ◽

Cmos Technology ◽

Circuit Implementation ◽

Power Requirement ◽

Cardiac Pacemakers ◽

Ultra Low Power ◽

System Synthesis

Abstract A high performance, ultra-low power, fully differential 2nd-order continuous-time ΣΔ analogue-to-digital modulator for cardiac pacemakers is presented in this paper. The entire design procedure is described in detail from the high-level system synthesis in both discrete and continuous-time domain, to the low-level circuit implementation of key functional blocks of the modulator. The power consumption of the designed modulator is rated at 182 nA from a 1.2V power supply, meeting the ultra-low power requirement of the cardiac pacemaker applications. A 65 nm CMOS technology is employed to implement the ΣΔ modulator. The modulator achieves a simulated SNR of 53.8 dB over a 400Hz signal bandwidth, with 32KHz sampling frequency and an oversampling ratio of 40. The active area of the modulator is 0.45 × 0.50mm2

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A low-power continuous-time incremental 2nd-order-MASH ΣΔ-modulator for a CMOS imager

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) ◽

10.1109/icecs.2009.5410946 ◽

2009 ◽

Cited By ~ 2

Author(s):

Johannes Uhlig ◽

Rene Schuffny ◽

Harald Neubauer ◽

Johann Hauer ◽

Joachim Haase

Keyword(s):

Low Power ◽

Continuous Time ◽

Cmos Imager ◽

Σδ Modulator

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A Low-Power ΣΔ Modulator Using Asynchronous SAR Quantizer for Sensor Application

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.482-484.241 ◽

2012 ◽

Vol 482-484 ◽

pp. 241-244

Author(s):

Wei Lang ◽

Pei Yuan Wan ◽

Ping Fen Lin

Keyword(s):

Power Consumption ◽

Low Power ◽

Input Signal ◽

Operational Amplifier ◽

Cmos Technology ◽

Analog Input ◽

Loop Topology ◽

Σδ Modulator ◽

Asynchronous Sar ◽

Reduced Power Consumption

This paper presents a low power ΣΔ modulator for a low power microsensor application. The ΣΔ modulator adopts second-order single loop topology with input feed-forward path. An asynchronous 4-bit successive approximation (SAR) quanztizer is employed to digitize the analog input. Inherent summation of SAR quantizer is utilized as analog summation. The switched operational amplifier is used in first integrator to reduced power consumption. The modulator, simulated at the transistor level using 0.13-μm CMOS technology, obtains a peak SNDR of 93 dB over an input signal of 5 kHz and simulation power consumption is 340 μW from 1-V supply.

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