High-sensitivity ultra-low-power electrode resistance monitoring circuit for cardiac pacemakers

2021 ◽  
Author(s):  
Jiangtao Xu ◽  
Zehong Yu ◽  
Yawei Wang ◽  
Ruizhi Zhang ◽  
Hong Zhang
Keyword(s):  
Low Power ◽  
High Sensitivity ◽  
Cardiac Pacemakers ◽  
Ultra Low Power ◽  
Resistance Monitoring ◽  
Electrode Resistance

Microcavity assisted acoustic wave channeling can lead to high sensitivity and ultra-low power SAW sensors

2015 ◽  
Author(s):  
Sina Koochakzadeh ◽  
Mandek Richardson ◽  
Venkat R. Bhethanabotla ◽  
Subramanian K. R. S. Sankaranarayanan
Keyword(s):  
Acoustic Wave ◽  
Low Power ◽  
High Sensitivity ◽  
Ultra Low Power

scholarly journals A configurable fluorescence sensing front-end for ultra-low power and high sensitivity applications

2021 ◽  
Author(s):  
Maryam Rafati ◽  
Seyed Ruhallah Qasemi ◽  
Atila Alvandpour
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Excitation Frequency ◽  
Average Power ◽  
High Sensitivity ◽  
Current Noise ◽  
Fluorescence Sensing ◽  
Ultra Low Power ◽  
Front End ◽  
Average Power Consumption

AbstractThis paper presents an ultra-low power, high sensitivity configurable CMOS fluorescence sensing front-end for implantable biosensors at single-cell level measurements. The front-end is configurable by a set of switches and consists of three integrated photodiodes (PD), three transimpedance amplifiers (TIA) for detecting a current range between 1 pA up to 10 mA. Also, an ambient light canceling technique is proposed to make the sensor operate under different environmental conditions. The proposed front-end could be configured for ultra-low light detection or ultra-low power consumption. The circuit is designed and fabricated in a 0.35 µm standard CMOS technology, and the measurement results are presented. The minimum integrated input-referred current noise is measured as 1.07 pA with the total average power consumption of 61.8 µW at an excitation frequency of 80 Hz. For ultra-low-power configuration, the front-end has an average power consumption of 119 nW and input integrated current noise of 210 pA at an excitation frequency of 20 kHz.

Design of an Ultra-Low Power CT ΣΔ A/D Modulator in 65 nm CMOS for Cardiac Pacemakers: From System Synthesis to Circuit Implementation

2014 ◽  
Vol 60 (1) ◽  
pp. 98-104 ◽  
Author(s):  
Yelin Wang ◽  
Hao Cai
Keyword(s):  
Low Power ◽  
Continuous Time ◽  
Cardiac Pacemaker ◽  
Design Procedure ◽  
Cmos Technology ◽  
Circuit Implementation ◽  
Power Requirement ◽  
Cardiac Pacemakers ◽  
Ultra Low Power ◽  
System Synthesis

Abstract A high performance, ultra-low power, fully differential 2nd-order continuous-time ΣΔ analogue-to-digital modulator for cardiac pacemakers is presented in this paper. The entire design procedure is described in detail from the high-level system synthesis in both discrete and continuous-time domain, to the low-level circuit implementation of key functional blocks of the modulator. The power consumption of the designed modulator is rated at 182 nA from a 1.2V power supply, meeting the ultra-low power requirement of the cardiac pacemaker applications. A 65 nm CMOS technology is employed to implement the ΣΔ modulator. The modulator achieves a simulated SNR of 53.8 dB over a 400Hz signal bandwidth, with 32KHz sampling frequency and an oversampling ratio of 40. The active area of the modulator is 0.45 × 0.50mm2

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