Introduction:
A new analytical model is designed for Workfunction Modulated Rectangular
Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove
gate and implements an idea of workfunction engineering.
Methods:
The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device
performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and
threshold voltage.
Results:
The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon
On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region.
Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage
is estimated in terms of minimum surface potential.
Conclusion:
In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential
and the drain current are also evaluated. It is observed from the analysis that the analog switching performance
of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability,
high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are
simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.
High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model
