An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

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Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

Journal of Nanotechnology ◽

10.1155/2019/4935073 ◽

2019 ◽

Vol 2019 ◽

pp. 1-12 ◽

Cited By ~ 1

Author(s):

Anjali Priya ◽

Nilesh Anand Srivastava ◽

Ram Awadh Mishra

Keyword(s):

Threshold Voltage ◽

Propagation Delay ◽

Silicon On Insulator ◽

Device Performance ◽

Gate Length ◽

Metal Gate ◽

Short Channel ◽

Fully Depleted ◽

Soi Mosfet ◽

Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

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Analytical model for the threshold voltage of dual material gate (DMG) partially depleted SOI MOSFET and evidence for reduced short-channel effects

Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004. ◽

10.1109/icsict.2004.1436745 ◽

2005 ◽

Author(s):

M. Jagidesh Kumar ◽

G. Venkateshwar Reddy

Keyword(s):

Analytical Model ◽

Threshold Voltage ◽

Short Channel Effects ◽

Short Channel ◽

Soi Mosfet ◽

Channel Effects ◽

Dual Material

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Analytical Modeling for Short Channel SOI-MOSFET and to Study its Performance

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.110-116.5150 ◽

2011 ◽

Vol 110-116 ◽

pp. 5150-5154

Author(s):

K. Senthil Kumar ◽

Saptarsi Ghosh ◽

Anup Sarkar ◽

S. Bhattacharya ◽

Subir Kumar Sarkar

Keyword(s):

Low Power ◽

Threshold Voltage ◽

Cmos Technology ◽

Current Drive ◽

Silicon On Insulator ◽

Short Channel Effects ◽

Short Channel ◽

Soi Mosfet ◽

Silicon Bulk ◽

Channel Effects

With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in VLSI circuit design. Conventional silicon (bulk CMOS) technology couldn‘t overcome the fundamental physical limitations belonging to sub-micro or nanometer region which leads to alternative device technology like Silicon-on-Insulator (SOI) technology. In a fully-depleted FDSOI structure the electrostatic coupling of channel with source/drain and substrate through the buried layer (BL) is reduced. This allows in turn to reduce the minimal channel length of transistors or to relax the requirements on Si film thickness. A generalized compact threshold voltage model for SOI-MOSFET is developed by solving 2-D Poisson‘s equation in the channel region and analytical expressions are also developed for the same. The performance of the device is evaluated after incorporating the short channel effects. It is observed that in SOI, presence of the oxide layer resists the short channel effects and reduces device anomalies such as substrate leakage by a great factor than bulk-MOS. The threshold voltage and current drive make SOI the ultimate candidate for low power application. Thus SOI-MOSFET technology could very well be the solution for further ultra scale integration of devices and improvised performance.

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Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET

Journal of Circuits System and Computers ◽

10.1142/s0218126618500639 ◽

2017 ◽

Vol 27 (04) ◽

pp. 1850063 ◽

Cited By ~ 5

Author(s):

Rajneesh Sharma ◽

Rituraj S. Rathore ◽

Ashwani K. Rana

Keyword(s):

Dielectric Materials ◽

Channel Length ◽

Silicon On Insulator ◽

Device Performance ◽

Short Channel ◽

Fully Depleted ◽

Soi Mosfet ◽

Channel Effects ◽

The Impact ◽

Gate Underlap

The fully depleted Silicon-On-Insulator MOSFETs (FD-SOI) have shown high immunity to short channel effects compared to conventional bulk MOSFETs. The inclusion of gate underlap in SOI structure further improves the device performance in nanoscale regime by reducing drain induced barrier lowering and leakage current ([Formula: see text]). However, the gate underlap also results in reduced ON current ([Formula: see text]) due to increased effective channel length. The use of high-[Formula: see text] material as a spacer region helps to achieve the higher [Formula: see text] but at the cost of increased effective gate capacitance ([Formula: see text]) which degrades the device performance. Thus, the impact of high-[Formula: see text] spacer on the performance of underlap SOI MOSFET (underlap-SOI) is studied in this paper. To fulfil this objective, we have analyzed the performance parameters such as [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text]/[Formula: see text] ratio and intrinsic transistor delay (CV/I) with respect to the variation of device parameters. Various dielectric materials are compared to optimize the [Formula: see text]/[Formula: see text] ratio and CV/I for nanoscale underlap-SOI device. Results suggest that the HfO2 of 10[Formula: see text]nm length is optimum value to enhance device performance. Further, the higher underlap length is needed to offset the exponential increase in [Formula: see text] especially below 20[Formula: see text]nm gate length.

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Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v12i2.458 ◽

2017 ◽

Vol 12 (2) ◽

pp. 101-106

Author(s):

V. T. Itocazu ◽

K. R. A. Sasaki ◽

V. Sonnenberg ◽

J. A. Martino ◽

E. Simoen ◽

...

Keyword(s):

Experimental Data ◽

Analytical Model ◽

Threshold Voltage ◽

Quantum Confinement ◽

Quantum Confinement Effect ◽

Silicon On Insulator ◽

Dynamic Threshold ◽

Fully Depleted ◽

Soi Mosfet ◽

Good Agreement

This paper presents an analytical model to determine the threshold voltage in Ultrathin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FD SOI) MOSFETs operating in dynamic threshold (DT) voltage modes. The analytical model is based on implementing the quantum confinement effect and the DT restriction. The results show that the proposed analytical model in its simplicity provides a good agreement to the experimental data.

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STUDY OF ELECTRICAL CHARACTERISTIC FOR 50NM AND 10NM SOI BODY THICKNESS IN MOSFET DEVICE

Jurnal Teknologi ◽

10.11113/jt.v77.6616 ◽

2015 ◽

Vol 77 (21) ◽

Author(s):

M.N.I.A Aziz ◽

F. Salehuddin ◽

A.S.M. Zain ◽

K.E. Kaharudin

Keyword(s):

Thin Film ◽

Electrical Characteristic ◽

Silicon On Insulator ◽

Electrical Characteristics ◽

Short Channel ◽

Doping Density ◽

Soi Mosfet ◽

Buried Oxide ◽

Soi Technology ◽

Better Than

Silicon-on-insulator (SOI) technology is an effective approach of mitigating the short channel effect (SCE) problems. The SOI is believed to be capable of suppressing the SCE, thereby improving the overall electrical characteristics of MOSFET device. SCE in SOI MOSFET is heavily influenced by thin film thickness, thin-film doping density and buried oxide (BOX) thickness. This paper will analyze the effect of BOX towards SOI MOSFET device. The 50nm and 10nm thickness of buried oxide in SOI MOSFET was developed by using SILVACO TCAD tools, specifically known as Athena and Atlas modules. From the observation, the electrical characteristic of 100nm thickness is slightly better than 50nm and 10nm. It is observed that the value drive current of 10nm and 100nm thickness SOI MOSFET was 6.9% and 11% lower than 50nm respectively, but the overall 50nm is superior. However, the electrical characteristics of 10nm SOI MOSFET are still closer and within the range of ITRS 2013 prediction.

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