A hierarchical design methodology for full-search block matching motion estimation

2006 ◽  
Vol 17 (4) ◽  
pp. 327-341 ◽  
Author(s):  
Mohamed Rehan ◽  
M. Watheq El-Kharashi ◽  
Fayez Gebali
Keyword(s):  
Motion Estimation ◽  
Design Methodology ◽  
Block Matching ◽  
Hierarchical Design ◽  
Full Search

LOW-POWER 2D MOTION ESTIMATION ARCHITECTURE WITH COMPLEMENTARY EMBEDDED MEMORY BANKS

2000 ◽  
Vol 10 (05n06) ◽  
pp. 229-237
Author(s):  
KYUNG-SAENG KIM ◽  
KWYRO LEE
Keyword(s):  
Motion Estimation ◽  
Data Transfer ◽  
Power Saving ◽  
Block Matching ◽  
Embedded Memory ◽  
Data Transfer Rate ◽  
Matching Algorithm ◽  
Block Matching Algorithm ◽  
Data Reading ◽  
Full Search

This letter describes a motion estimation architecture with complementary access types of memory banks, one for column vector access and the other for row vector access. It handles 2D image very efficiently for full-search block matching algorithm and maximizes a useful data transfer rate by reducing the overhead clocks for extra data reading and alignment. The results show that power saving is improved by using complementary access types of memory banks and amounts to 27.3% when the full-search block matching algorithm is applied for the CCIR-601 format compared to an identical design without the proposed enhancements.

High Performance Architecture of Motion Estimation Algorithm for Video Compression

2016 ◽  
Vol 25 (08) ◽  
pp. 1650083
Author(s):  
P. Muralidhar ◽  
C. B. Rama Rao
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
High Performance ◽  
Estimation Algorithm ◽  
Block Matching ◽  
High Definition ◽  
Systolic Architecture ◽  
Hardware Architectures ◽  
Computationally Intensive ◽  
Full Search

Motion estimation (ME) is a highly computationally intensive operation in video compression. Efficient ME architectures are proposed in the literature. This paper presents an efficient low computational complexity systolic architecture for full search block matching ME (FSBME) algorithm. The proposed architecture is based on one-bit transform-based full search (FS) algorithm. The proposed ME hardware architectures perform FS ME for four macroblocks (MBs) in parallel. The proposed hardware architecture is implemented in VHDL. The FSBME hardware consumes 34% of the slices in a Xilinx Vertex XC6vlx240T FPGA device with a maximum frequency of 133[Formula: see text]MHz and is capable of processing full high definition (HD) ([Formula: see text]) frames at a rate of 60 frames per second.

FAST MOTION ESTIMATION SCHEME FOR VIDEO CODING USING FEATURE VECTOR MATCHING AND MOTION VECTOR'S CORRELATIONS

1999 ◽  
Vol 09 (01n02) ◽  
pp. 67-82
Author(s):  
TINGRONG ZHAO ◽  
MASAO YANAGISAWA ◽  
TATSUO OHTSUKI
Keyword(s):  
Computational Complexity ◽  
Motion Estimation ◽  
Block Matching ◽  
Boolean Logic ◽  
Phase Matching ◽  
Data Set ◽  
Pixel Intensity ◽  
Binary Phase ◽  
Estimation Scheme ◽  
Full Search

In this paper, we propose a fast block motion estimation scheme by exploiting the correlations of motion vectors (MV) existing in spatially- and temporally-adjacent as well as hierarchically-related blocks. The basic idea is to use the information obtained from the corresponding block at a coarser resolution level and spatio-temporal neighboring blocks at the same level in order to select a good set of initial MV candidates and then perform further local search to find the best matching MV. In order to further reduce computational complexity, the sign pattern vector (SPV) is defined and used for block matching, as opposed to the pixel intensity values used in the conventional block matching methods. By using the SPV definition, a data block can be presented by a mean and a set of binary sign patterns with a much reduced data set. The block matching motion estimation is then divided into mean matching and binary phase matching. The proposed technique enables a significant reduction in computational complexity compared with the conventional block matching motion estimation (ME) because binary phase matching only involves Boolean logic operations. This scheme also significantly reduces the data transfer time between the frame buffer and motion estimator. Our test results indicate that the performance of the proposed scheme is comparable with the full-search block matching under the same search ranges, however, the proposed scheme has a speed-up factor ranging from 250 to 370 in comparison with full search.

A programmable motion estimation processor for full search block matching

2002 ◽  
Author(s):  
A. Pirson ◽  
F. Yassa ◽  
P. Paul ◽  
B. Canfield ◽  
F. Rominger ◽  
...  
Keyword(s):  
Motion Estimation ◽  
Block Matching ◽  
Full Search
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