Joint MAP Detection for OFDM in Presence of Phase Noise from Free Running and Phase Locked Loop Oscillator

2019 ◽  
Vol 109 (1) ◽  
pp. 563-577
Author(s):  
Kamayani Shrivastav ◽  
R. P. Yadav ◽  
K. C. Jain
Keyword(s):  
Phase Noise ◽  
Phase Locked Loop ◽  
Free Running

Phase Noise Measurement of Optical Heterodyning Two-Tone Signal Generated by Two Free-Running Lasers

2013 ◽  
Vol E96.C (2) ◽  
pp. 241-244
Author(s):  
Ryuta YAMANAKA ◽  
Taka FUJITA ◽  
Hideyuki SOTOBAYASHI ◽  
Atsushi KANNO ◽  
Tetsuya KAWANISHI
Keyword(s):  
Phase Noise ◽  
Noise Measurement ◽  
Tone Signal ◽  
Free Running

Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

Phase Noise in Millimeter Wave Phase-Locked Loop with Mixer

2007 ◽  
Vol 28 (4) ◽  
pp. 299-304 ◽  
Author(s):  
Yonghong Zhang ◽  
Yong Fan ◽  
Zhengde Wu
Keyword(s):  
Phase Noise ◽  
Millimeter Wave ◽  
Phase Locked Loop ◽  
Wave Phase

Design of microwave signal source for CS chip-scale atomic clock

2017 ◽  
Vol 31 (07) ◽  
pp. 1741010 ◽  
Author(s):  
Ji Lei ◽  
Meng Hui Zhi ◽  
Xin Wei Li ◽  
Tang Liang ◽  
Dong Hai Qiao
Keyword(s):  
Phase Noise ◽  
Low Temperatures ◽  
Good Condition ◽  
Atomic Clock ◽  
Phase Locked Loop ◽  
Microwave Signal ◽  
Coherent Population Trapping ◽  
Signal Source ◽  
Loop Filter ◽  
High And Low Temperatures

Nowadays, some countries have already invented chip-scale atomic clock (CSAC) based on coherent population trapping (CPT), and it has been applied in every areas. According to its working principle, the microwave signal source is one of the decisive factors affecting its stability. Usually the microwave signal source is a phase-locked loop circuit, it mainly includes a frequency synthesizer, a voltage controlled oscillator (VCO) and a loop filter. This paper aims to develop a microwave signal source for Cs CSAC. First, a VCO should be designed, in order to validate the characteristic of the designed VCO, the VCO needs to be tested at high and low temperatures, and the results show that it has good stability of high and low temperatures. Second, for the purpose of verifying that the design and production consistency of the VCO are in good condition, 1000 VCOs are test, respectively. The statistical distribution of the phase noise at 1 kHz offset would be painted a curve. Finally, the designed VCO (PN: 61.01dBc/Hz@1kHz) will be applied in phase-locked loop, the test results show that the phase noise is −83.57dBc/Hz@300Hz, it is much better than −43dBc/Hz@300Hz which is the spec of CSAC. If the microwave signal source would be used in CSAC, its stability would be greatly improved.

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