An adaptive random access strategy for multi-channel relaying networks

2009 ◽  
Vol 52 (12) ◽  
pp. 2406-2414 ◽  
Author(s):  
Fan Jiang ◽  
Hui Tian ◽  
Ping Zhang
Keyword(s):  
Random Access ◽  
Relaying Networks

Multichannel Random Access Protocol with Capture Effect for Cellular Relaying Networks

2010 ◽  
Vol E93-B (11) ◽  
pp. 3093-3101
Author(s):  
Sunghyun CHO ◽  
Young-Ho JUNG ◽  
Cheolwoo YOU
Keyword(s):  
Random Access ◽  
Capture Effect ◽  
Access Protocol ◽  
Random Access Protocol ◽  
Relaying Networks

Modern Random Access Protocols

2016 ◽  
Author(s):  
Matteo Berioli ◽  
Giuseppe Cocco ◽  
Gianluigi Liva ◽  
Andrea Munari
Keyword(s):  
Random Access ◽  
Access Protocols

Comparative Assessment of Optical Techniques for Semi-Invasive SRAM Data Read-out on an MSP430 Microcontroller

2018 ◽  
Author(s):  
Tuba Kiyan ◽  
Heiko Lohrke ◽  
Christian Boit
Keyword(s):  
Supply Voltage ◽  
Photon Emission ◽  
Random Access ◽  
Integration Time ◽  
Security Evaluation ◽  
Testing And Debugging ◽  
Advantages And Disadvantages ◽  
The Core ◽  
Voltage Signal ◽  
Chip Testing

Abstract This paper compares the three major semi-invasive optical approaches, Photon Emission (PE), Thermal Laser Stimulation (TLS) and Electro-Optical Frequency Mapping (EOFM) for contactless static random access memory (SRAM) content read-out on a commercial microcontroller. Advantages and disadvantages of these techniques are evaluated by applying those techniques on a 1 KB SRAM in an MSP430 microcontroller. It is demonstrated that successful read out depends strongly on the core voltage parameters for each technique. For PE, better SNR and shorter integration time are to be achieved by using the highest nominal core voltage. In TLS measurements, the core voltage needs to be externally applied via a current amplifier with a bias voltage slightly above nominal. EOFM can use nominal core voltages again; however, a modulation needs to be applied. The amplitude of the modulated supply voltage signal has a strong effect on the quality of the signal. Semi-invasive read out of the memory content is necessary in order to remotely understand the organization of memory, which finds applications in hardware and software security evaluation, reverse engineering, defect localization, failure analysis, chip testing and debugging.

Yield Enhancement Study: Process Variation and Design Margins Leading to Timing Issues in the RAM

2000 ◽  
Author(s):  
Srikanth Perungulam ◽  
Scott Wills ◽  
Greg Mekras
Keyword(s):  
Cross Sections ◽  
Digital Signal Processor ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Digital Signal ◽  
Yield Enhancement ◽  
Final Conclusion ◽  
Stage Separation ◽  
Study Process

Abstract This paper illustrates a yield enhancement effort on a Digital Signal Processor (DSP) where random columns in the Static Random Access Memory (SRAM) were found to be failing. In this SRAM circuit, sense amps are designed with a two-stage separation and latch sequence. In the failing devices the bit line and bit_bar line were not separated far enough in voltage before latching got triggered. The design team determined that the sense amp was being turned on too quickly. The final conclusion was that a marginal sense amp design, combined with process deviations, would result in this type of failure. The possible process issues were narrowed to variations of via resistances on the bit and bit_bar lines. Scanning Electron Microscope (SEM) inspection of the the Focused Ion Beam (FIB) cross sections followed by Transmission Electron Microscopy (TEM) showed the presence of contaminants at the bottom of the vias causing resistance variations.

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

1998 ◽  
Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Temperature Sensitive ◽  
Wafer Level ◽  
Top Down ◽  
Access Memory ◽  
Transmission Electron ◽  
Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

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