Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures

2010 ◽  
Vol 50 (9-11) ◽  
pp. 1636-1640 ◽  
Author(s):  
Y. Yang ◽  
R. Labie ◽  
F. Ling ◽  
C. Zhao ◽  
A. Radisic ◽  
...  
2020 ◽  
Vol 12 ◽  
Author(s):  
Kang-Jia Wang ◽  
Hong-Chang Sun ◽  
Kui-Zhi Wang

Background: With the increase of the integration degree of the three-dimensional integrated circuit(3D IC), the thermal power consumption per unit volume increases greatly, which makes the chip temperature rise. High temperature could affect the performance of the devices and even lead to thermal failure. So, the thermal management for 3D ICs is becoming a major concern. Objective: The aim of the research is to establish a micro-channel cooling model for a three-dimensional integrated circuit(3D IC) considering the through-silicon vias(TSVs). Methods: By studying the structure of the TSVs, the equivalent thermal resistance of each layer is formulated. Then the one-dimensional micro-channel cooling thermal analytical model considering the TSVs was proposed and solved by the existing sparse solvers such as KLU. Results: The results obtained in this paper reveal that the TSVs can effectively improve the heat dissipation, and its maximal temperature reduction is about 10.75%. The theoretical analysis is helpful to optimize the micro-channel cooling system for 3D ICs. Conclusion: The TSV has an important influence on the heat dissipation of 3D IC, which can improve its heat dissipation characteristic


Author(s):  
Xi Liu ◽  
Qiao Chen ◽  
Venkatesh Sundaram ◽  
Sriram Muthukumar ◽  
Rao R. Tummala ◽  
...  

Through-silicon vias (TSVs), being one of the key enabling technologies for 3D system integration, are being used in various 3D vertically stacked devices. As TSVs are relatively new, there is not enough information in available literature on the thermo-mechanical reliability of TSVs. Due to the high coefficient of thermal expansion (CTE) mismatch between Si and the Cu vias, “Cu pumping” will occur at high temperature and “Cu sinking” will occur at low temperature, which may induce large stress in SiO2, interfacial stress at Cu/SiO2 interface and plastic deformation in Cu core. The thermal-mechanical stress can potentially cause interfacial debonding, cohesive cracking in dielectric layers or Cu core, causing some reliability issues. Thus, in this paper, three-dimensional thermo-mechanical finite-element models have been built to analyze the stress/strain distribution in the TSV structures. A comparative analysis of different via designs, such as circular, square, and annular vias has been performed. In addition, defects due to fabrication such as voids in the Cu core during electroplating and Cu pad undercutting due to over-etching are considered in the models, and it is seen that these fabrication defects are detrimental to TSV reliability.


Author(s):  
Ronald Hon ◽  
Shawn X. D. Zhang ◽  
S. W. Ricky Lee

The focus of this study is on the fabrication of through silicon vias (TSV) for three dimensional packaging. According to IPC-6016, the definition of microvias is a hole with a diameter of less than or equal to 150 μm. In order to meet this requirement, laser drilling and deep reactive ion etching (but not wet etching) are used to make the microvias. Comparisons between these two different methods are carried out in terms of wall straightness, smoothness, smallest via produced and time needed for fabrication. In addition, discussion on wafer thinning for making through silicon microvias is given as well.


2012 ◽  
Vol 100 (4) ◽  
pp. 041901 ◽  
Author(s):  
Suk-Kyu Ryu ◽  
Tengfei Jiang ◽  
Kuan H. Lu ◽  
Jay Im ◽  
Ho-Young Son ◽  
...  

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