Reliable Design of Electroplated Copper Through Silicon Vias

Through-silicon vias (TSVs), being one of the key enabling technologies for 3D system integration, are being used in various 3D vertically stacked devices. As TSVs are relatively new, there is not enough information in available literature on the thermo-mechanical reliability of TSVs. Due to the high coefficient of thermal expansion (CTE) mismatch between Si and the Cu vias, “Cu pumping” will occur at high temperature and “Cu sinking” will occur at low temperature, which may induce large stress in SiO2, interfacial stress at Cu/SiO2 interface and plastic deformation in Cu core. The thermal-mechanical stress can potentially cause interfacial debonding, cohesive cracking in dielectric layers or Cu core, causing some reliability issues. Thus, in this paper, three-dimensional thermo-mechanical finite-element models have been built to analyze the stress/strain distribution in the TSV structures. A comparative analysis of different via designs, such as circular, square, and annular vias has been performed. In addition, defects due to fabrication such as voids in the Cu core during electroplating and Cu pad undercutting due to over-etching are considered in the models, and it is seen that these fabrication defects are detrimental to TSV reliability.

Thermally Based Design Optimization of Telecommunication Shelter

Telecommunication shelters are generally used for housing the electronic equipments and are an integral component at various levels of wireless access networks. The electronics which dissipate heat needs to be cooled for proper functioning of the equipment. Telecom shelters are generally stand-alone, modular structures with their own electrical HVAC systems. The effect of cabinet’s location in the shelter on temperature is studied. The outline of the paper is to validate the shelter model with the test data available by using CFD tool and perform thermal analysis for different location of 2G cabinets and then, to study the effect of isolation in the shelter. It is observed that the isolation in the shelter attributes to lowering the temperature of the cabinets.

Recent Advancement on Liquid Metal Cooling for Thermal Management of Computer Chip

Efficient cooling of a high performance computer chip has been an extremely important however becoming more and more tough issue. The recently invented liquid metal cooling method is expected to pave the way for high flux heat dissipation which is hard to tackle otherwise by many existing conventional cooling strategies. However, as a new thermal management method, its application also raised quite a few challenging fundamental and practical issues for solving. To illustrate the development of the new technology, this talk is dedicated to present an overview on the latest advancements made in the author’s lab in developing the new generation chip cooling device based on the liquid metal coolant with melting point around room temperature. The designing and optimization of the cooling device and component will be discussed. Several major barriers to prevent the new method from practical application such as erosion between liquid metal coolant and its substrate material will be outlined with good solutions clarified. Performance comparison between the new chip cooling method with commercially available products with highest quality such as air cooling, water cooling and heat pipe cooling devices were evaluated. Typical examples of using liquid metal cooling for the thermal management of a real PC or even super computer will be demonstrated. Further, miniaturizations on the prototype device by extending it as a MEMS cooling device or mini/micro channel liquid metal cooling device will also be explained. Along with the development of the hardware, some fundamental heat transfer issues in characterizing the liquid metal cooling device will be discussed through numerical or analytical model. Future challenging issues in pushing the new technology into large scale practices will be raised. From all the outputs obtained so far, it can be clearly seen that the new cooling strategy will find very promising and significant applications in a wide variety of engineering situations whenever thermal managements or heat transport are needed.

Topological Design Optimization of Nested Channels for Squeeze Flow of Thermal Interface Materials

Thermal interface resistance remains a bottleneck for thermal transport in electronic systems, comprising a significant portion of overall system thermal resistance. Performance of thermal interface materials (TIMs) is largely dependent on the bulk thermal conductivity of the TIM but also on the bond-line thickness (BLT) of the applied material as well as interfacial contact resistances. Recently, Hierarchically Nested Channels (HNCs), created by modifying the surface topology with hierarchical arrangements of microchannels in order to improve flow, were proposed to reduce both required squeezing force and final BLTs in interfaces. In this paper, a topological optimization framework that enables the design of channel arrangements is developed. The framework is based on a resistance network approximation to Newtonian squeeze flow. The approximation, validated against finite element method (FEM)-based solutions, allows efficient, design-oriented solutions for squeeze flow in complex geometries. A comprehensive design sensitivity analysis exploiting the resistance network approximation is also developed and implemented. The resistance approximation and the sensitivity analysis is used to build an automated optimal channel design framework. A Pareto optimal problem formulation for the design of channels is posed and the optimal solution is demonstrated using the framework.

An Evaluation of a Modified Iosipescu Specimen for Measurement of Elastic-Plastic Properties of Solder Materials

There are various specimen configurations available in the literature for characterizing the mechanical behavior of solder interconnect materials. An ideal test specimen should use a simple geometry to minimize the complexity of the stress analysis and which produces a uniform material response throughout the test material. In the thermo-mechanical micro scale (TMM) test used in this study, we use a simple, notched shear specimen, based on a concept originally proposed by Iosipescu [1967] [1], which produces a very uniform shear stress field in the solder joint volume [Reinikainen et al., 1998] [2]. Our modified Iosipescu specimen comprises of two oxygen free, high conductivity (OFHC) copper platens soldered together and loaded in simple shear. The solder joint in this specimen is only 180 microns wide to capture the length scale effects of functional solder interconnects. This study examines the effects of dimensional variabilities of this modified Iosipescu specimen on the shear stress distribution in the solder joint. Variabilities encountered in these specimens include: (i) fillets at the V-notches, caused by excess solder; (ii) offset between the two copper platens along the loading direction; (iii) taper of the solder joint due to lack of parallelism of the edges of the copper platens; and (iv) misalignment between the specimen centerline and loading axis of the TMM test frame due to mounting variability. Detailed parametric studies of these four dimensional variations in the TMM specimen are conducted using a simple two-dimensional elastic-plastic finite element model. The uniformity of the shear stress field in the specimen is investigated and the variation in the derived stress-strain curves is examined, as a function of the dimensional variabilities described above.

Nanostructure Dependence of the Electronic Conductivity of Carbon Nanotubes and Graphene Sheets

In this study, the change of the resistivity of the CNT-dispersed resin was analyzed by applying a quantum chemical molecular dynamics and the first principle calculation. Various combinations of double-walled carbon nanotube structures were modeled for the analysis. The change of the band structure was calculated by changing the amplitude of the applied strain. It was found in some cases that the band structure changes drastically from a metallic structure to a semiconductive structure, and this result clearly indicated that the electronic conductivity of this MWCNT decreased significantly under tensile strain. It was also found that further application of the strain made a band gap in the band structure. This result indicated that the metallic CNT changes a semiconductive CNT due to the applied strain. The effect of the diameter of the zigzag type CNT on the critical strain of buckling deformation was analyzed under a uni-axial strain. In this analysis, the aspect ratio of each structure was fixed at 10. It was found that the critical strain decreased monotonically with the increase of the diameter. This was because that the flexural rigidity of a cylinder decreased with the increase of its diameter when the thickness of the wall of the cylinder is fixed. It was found that the critical strain decreased drastically from about 5% to 0.5% when the aspect ratio was changed from 10 to 30. Since the typical aspect ratio of CNTs often exceeds 1000, most CNTs show buckling deformation when an axial compressive strain was applied to the CNTs. Finally, the shape of six-membered ring of the CNT was found to be the dominant factor that determines the electronic band structure of a CNT. Next, the change of the band structure of a graphene sheet was analyzed by applying the abinitio calculation (Density functional theory). It was found that the fluctuation of the atomic distance among the six-membered ring is the most dominant factor of the electronic band structure. When the fluctuation exceeded about 10%, band gap appeared in the deformed six-membered ring, and thus, the electronic conductivity of the graphene sheet changes from metallic one to semiconductive one. It is therefore, possible to predict the change of the electronic conductivity of a CNT by considering the local shape of a six-membered ring in the deformed CNT.

Fatigue Strength of Ribbon Bonds

Ribbon or wire bonding is a common manufacturing process used in the microelectronic industry to make interconnections between electronic components. This process is used because it can make up for misalignment and inconsistent spacing between the components due to tolerance stack ups. In addition, since the ribbons are not rigid they will flex and absorb any stresses that develop when the components expand and contract in the field due to temperature changes. This paper investigates the use of a mechanical method to exercise ribbons in this fashion until they failed. Ribbons of a constant profile but different sizes were exercised at different levels of stress to develop a fatigue life model. It is found that ribbons exercised only a small percentage of their overall span survive exponentially longer than the same ribbons exercised at a higher percentage of their overall span. In addition, at short span lengths relative to the thickness, the ribbon becomes less ‘thread like’ and more stiff. The model developed in this study can be used for designing ribbon size and shape based upon expected thermal expansion cycling and necessary life or reliability.

Power Stack Die Package Design, Simulation and Reliability Analysis

This paper presents a power stack die package design for a point of load buck converter. The buck converter system in package (SiP) consists of a lower side Mosfet and a high side Mosfet together with an IC controller. Its structure includes a premolded leadframe with an IC controller. The two Mosfets (both low side and higher side) are stacked on the premolded leadfrrame (LF) and IC controller. Solder balls are placed on the leadframe’s exposed lands, and together with the two drains of Mosfets, to form the stacked die power package. The thermal cycling simulations for the solder balls to connect the PCB and solder joints of the two Mosfet die to the leadframe pads are studied. The failure mechanism and reliability analysis of the power package in TMCL test are discussed.

The Investigation of 3D Embedded Microchannel Networks for 3D IC Cooling, Vacuum Packaging and THz Passive Device Applications

This Paper reports the design, simulation and test of 3D microchannel networks intended for the 3D IC stackup cooling, vacuum building and even THz passive device applications. Recently, the prominent advantages of 3D IC integration, including reduction in system size, interconnect delay, power dissipation and enabling hyper-integration of chips from disparate process technologies, have drive the relentless research effort worldwide. Although various low-power methodologies are exploited, rapid increasing in device packing density in 3D stacking of chips have demanded revolutionary heat removal technologies, as high performance chips projected to dissipate more than 100W/cm2 and require more than 100A of supply current are frequently integrated. Besides, high data rate and bandwidth interconnects are urgently needed as an efficient data transfer backbone between the chips comprising 3D ICs. To address these limits, the authors investigated 3D microchannel networks with various layouts such as fractal tree, which is embedded into stackup structures for highly efficient cooling, and as THz (terahertz) range waveguides. The 3D microchannel networks, with water as working medium are designed and simulated with computational fluidic dynamic methodology, which reveals both the flow and temperature fields and verifies their effectiveness in 3D stackup structure cooling. The 3D microchannels are further experimentally validated on a fast microsystem prototyping platform based on laminating multiple layers of Low Temperature Cofired Ceramic plates, which is capable of quickly realizing a complex exterior or interior 3D structures, for experimental validation. A testing system is set up, consisting of resistive heating source, temperature pickup device and microfluidic metering pumping devices. The temperature rises for samples with or without 3D microchannels with different configurations under various heat flux are obtained and compared with simulated results. The testing results shows that this embedded microfluidic cooling technique may effectively realized a decrease of around 60 centigrade at a heat flux of 1W/cm2 and increase with the flux, confirming the effectiveness of this 3D microchannel in cooling a stackup structure and that of the simulation and modeling. Beside the microchannel, combined with sealed pipe I/O joints may effectively act as a ventilation pumping path for the vacuum buildup, adjustment and vacuum level inspection for 3D IC vacuum packaging. In addition, the authors present the investigations of the conceptional design of waveguide and functional structures operating at terahertz frequencies, together with the simulation results which demonstrate the prosperity of this simple structure for high data rate transmission in 3D IC stackups.

Conjugate Mixed Convection With Surface Radiation and Substrate Conduction in Laminar Channel Flow With Discrete Flush-Mounted Heat Sources

Thermal analysis employing a full conjugation model is performed in this study for laminar airflow in a parallel-plate channel with discrete flush-mounted heat sources. The numerical model accounts for mixed convection, surface radiation, and two-dimensional conduction in the substrate. The effects of Reynolds number, surface emissivity of walls and heat sources, as well as thickness and thermal conductivity of the substrate, are analyzed in detail. It is shown that participation of radiation brings the wall temperatures closer, and the trend of temperature variation along the top wall is drastically altered. Such effects are pronounced for black enclosures and diminished for high Reynolds numbers. The influence of substrate conductivity and thickness is very similar in that a large value for both parameters would facilitate redistribution of heat and tend to yield a uniform temperature field in the substrate. For highly conductive or thick substrate, the ‘hot spot’ cools down and may move upstream to the penultimate source. Radiation loss to the ambient increases with substrate conductivity and thickness due to the elevated temperature near the inlet and outlet, yet the total heat transfer over the bottom surface by convection and radiation remains unaltered.