Analysis of Eddy Effect for Cu and CNT Bundle Based Through-Silicon Vias: Impact on Crosstalk and Power

The performance of a three dimensional integrated circuit primarily depends on the filler material used in through silicon via (TSV). The mostly used filler material Cu is primarily facing severe reliability issues due to the skin effect and electromugration related problems at high frequencies. Therefore, in recent, single- and multi-walled carbon nanotubes (SWCNT and MWCNT) have been emerged as suitable filler materials in TSV. Additionally, at high frequencies, an electrmagetic force primarly induces to an eddy current that adversely affects the overall performance of a TSV. This paper for the first time demonstrates the impact of eddy current on Cu, bundled SWCNT and MWCNT based TSVs. An accurate RLGC circuit model is proposed by considering the eddy effect at the depletion layer and the silicon substrate region. The equivalent circuit parameters are modelled at 7 nm technology using a three line driver-via-load setup. Using the proposed setup, crosstalk and power disspation are analyzed with and without considering the eddy effect. Irrespective of TSV heights, the MWCNT bundle demonstrates substantially lower crosstalk delay, peak noise and power dissipation in comparison to the Cu and SWCNT bundle based TSVs.

Genetic Algorithms and Particle Swarm Optimization Mechanisms for Through-Silicon Via (TSV) Noise Coupling

In this paper, two intelligent methods which are GAs and PSO are used to model noise coupling in a Three-Dimensional Integrated Circuit (3D-IC) based on TSVs. These techniques are rarely used in this type of structure. They allow computing all the elements of the noise model, which helps to estimate the noise transfer function in the frequency and time domain in 3D complicated systems. Noise models include TSVs, active circuits, and substrate, which make them difficult to model and to estimate. Indeed, the proposed approaches based on GA and PSO are robust and powerful. To validate the method, comparisons among the results found by GA, PSO, measurements, and the 3D-TLM method, which presents an analytical technique, are made. According to the obtained simulation and experimental results, it is found that the proposed methods are valid, efficient, precise, and robust.

Thermal management of three-dimensional integrated circuits with special structures

Different stacked structures affect greatly the temperature distribution of a three-dimensional integrated circuit(3-D IC), and an optimal structure is much needed to reduce the maximal temperature. This paper suggests a numerical approach to such structures with different heat source distributions. The results show that an optimal stacked structure can reduce the maximum temperature by 8.7?C.

Fabrication of Low Cost and Low Temperature Poly-Silicon Nanowire Sensor Arrays for Monolithic Three-Dimensional Integrated Circuits Applications

In this paper, the poly-Si nanowire (NW) field-effect transistor (FET) sensor arrays were fabricated by adopting low-temperature annealing (600 °C/30 s) and feasible spacer image transfer (SIT) processes for future monolithic three-dimensional integrated circuits (3D-ICs) applications. Compared with other fabrication methods of poly-Si NW sensors, the SIT process exhibits the characteristics of highly uniform poly-Si NW arrays with well-controlled morphology (about 25 nm in width and 35 nm in length). Conventional metal silicide and implantation techniques were introduced to reduce the parasitic resistance of source and drain (SD) and improve the conductivity. Therefore, the obtained sensors exhibit >106 switching ratios and 965 mV/dec subthreshold swing (SS), which exhibits similar results compared with that of SOI Si NW sensors. However, the poly-Si NW FET sensors show the Vth shift as high as about 178 ± 1 mV/pH, which is five times larger than that of the SOI Si NW sensors. The fabricated poly-Si NW sensors with 600 °C/30 s processing temperature and good device performance provide feasibility for future monolithic three-dimensional integrated circuit (3D-IC) applications.

Study of Bonded Wafers by Using a Synchrotron Radiation Transmission X-ray Microscopy for Three-Dimensional Integrated Circuit

Synchrotron radiation transmission X-ray microscopy (SRTXM) was applied for visualization of the interfacial layer in bonded wafer pairs. The X-ray energy of 6.54 keV with a monitoring window was utilized to enhance a resolution of transmission X-ray microscopy (TXM). The monitoring window was designed a locally uncovered area of the bonded wafer pairs to make the thickness of bonded wafers less than 200 μm. The experimental results showed that the technique has sub-micron meter resolution. Also this technique can improve the resolution of the synchrotron X-ray for nanoelectronics application.

A Micro-channel Cooling Model For a Three-dimensional Integrated Circuit Considering Through-silicon Vias

Background: With the increase of the integration degree of the three-dimensional integrated circuit(3D IC), the thermal power consumption per unit volume increases greatly, which makes the chip temperature rise. High temperature could affect the performance of the devices and even lead to thermal failure. So, the thermal management for 3D ICs is becoming a major concern. Objective: The aim of the research is to establish a micro-channel cooling model for a three-dimensional integrated circuit(3D IC) considering the through-silicon vias(TSVs). Methods: By studying the structure of the TSVs, the equivalent thermal resistance of each layer is formulated. Then the one-dimensional micro-channel cooling thermal analytical model considering the TSVs was proposed and solved by the existing sparse solvers such as KLU. Results: The results obtained in this paper reveal that the TSVs can effectively improve the heat dissipation, and its maximal temperature reduction is about 10.75%. The theoretical analysis is helpful to optimize the micro-channel cooling system for 3D ICs. Conclusion: The TSV has an important influence on the heat dissipation of 3D IC, which can improve its heat dissipation characteristic

Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

Anisotropic Grain Growth in (111) Nanotwinned Cu Films by DC Electrodeposition

We have reported a method of fabricating (111)-orientated nanotwinned copper (nt-Cu) by direct current electroplating. X-ray analysis was performed for the samples annealed at 200 to 350 °C for an hour. X-ray diffraction indicates that the (200) signal intensity increases while (111) decreases. Abnormal grain growth normally results from transformation of surface energy or strain energy density. The average grain size increased from 3.8 µm for the as-deposited Cu films to 65–70 µm after the annealing at 250 °C for 1 h. For comparison, no significant grain growth behavior was observed by random Cu film after annealing for an hour. This research shows the potential for its broad electric application in interconnects and three-dimensional integrated circuit (3D IC) packaging.

Performance Variation of Nano-Scaled Devices in 3D-IC Packaging Architecture Induced by TSV Residual Stress

Through-silicon via (TSV) technique, is widely adopted as the vertical interconnection technology of three-dimensional integrated circuit packaging architecture. However, fabrication process-induced residual stress occurred in TSV during annealing and introduced the subsequent thermal–mechanical stress into silicon-based interposer. Aforementioned residual stress will affect the performance and electric stability of p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) located around TSV. Accordingly, this study is focused on the influences of TSV layout with intrinsic residual stress on concerned pMOSFET performance. Process-oriented finite element analysis (FEA) is performed to simulate stress distribution of pMOSFET when concerned device channel region was affected by TSV residual stress and embedded SiGe alloy. To conquer the difficulty of FEA construction on TSV and pMOSFET with significant scale mismatch in same FEA model, the global–local submodeling technology is adopted to manage the balance between model complexity and numerical convergence. The residual stress magnitude effect of different designed TSV diameter on concerned channel stress components is extracted to estimate its influence on pMOSFET with scaled gate width. The presented results indicated that increased TSV residual stress could obviously reduce performance of concerned device. It should be noted that the S/D stressor remarkably dominated mobility gain of strained pMOSFET.