Pre-filtered and post-filtered 1-bit delta sigma modulator for fronthaul downlinks

2022 ◽  
pp. 127908
Author(s):  
Xiaoran Xie ◽  
Xiupu Zhang
Keyword(s):  
Delta Sigma Modulator ◽  
Delta Sigma

A Delta-Sigma Modulator Using a Non-uniform Quantizer Adjusted for the Probability Density of Input Signals

2012 ◽  
Vol E95.B (7) ◽  
pp. 2257-2265
Author(s):  
Toru KITAYABU ◽  
Mao HAGIWARA ◽  
Hiroyasu ISHIKAWA ◽  
Hiroshi SHIRAI
Keyword(s):  
Probability Density ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Input Signals

A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element-Shifting Dynamic Element Matching

2012 ◽  
Vol E95.C (6) ◽  
pp. 1017-1025
Author(s):  
Hong Phuc NINH ◽  
Masaya MIYAHARA ◽  
Akira MATSUZAWA
Keyword(s):  
Continuous Time ◽  
Dynamic Element Matching ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Dynamic Element

An Energy-Efficient ^|^Delta;^|^Sigma; Modulator Using Dynamic-Common-Source Integrators

2014 ◽  
Vol E97.C (5) ◽  
pp. 438-443 ◽  
Author(s):  
Ryo MATSUSHIBA ◽  
Hiroaki KOTANI ◽  
Takao WAHO
Keyword(s):  
Energy Efficient ◽  
Common Source ◽  
Delta Sigma Modulator ◽  
Delta Sigma

scholarly journals A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 177
Author(s):  
Dongjun Park ◽  
Sungwook Choi ◽  
Jongsun Kim
Keyword(s):  
Sampling Technique ◽  
Cmos Process ◽  
Detection Range ◽  
Delay Locked Loop ◽  
Delta Sigma Modulator ◽  
Correlated Double Sampling ◽  
Delta Sigma ◽  
Fast Power ◽  
Low Jitter ◽  
Reference Clock

An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.

A spread spectrum clock generator with a wide frequency and attenuation tuning range based on a third-order error-feedback delta-sigma modulator

2009 ◽  
Vol 65 (1) ◽  
pp. 115-121
Author(s):  
Jia Peng Zheng ◽  
Ruth Wei Li ◽  
Peng Ren ◽  
Yi Yang ◽  
Chien Chun Shao ◽  
...  
Keyword(s):  
Spread Spectrum ◽  
Tuning Range ◽  
Clock Generator ◽  
Error Feedback ◽  
Third Order ◽  
Order Error ◽  
Delta Sigma Modulator ◽  
Delta Sigma

116dB SFDR delta-sigma modulator with a novel GM-boost OPAMP for audio application

2014 ◽  
Author(s):  
Yongsheng Wang ◽  
Houchen Ji ◽  
Hongyin Wang ◽  
Lin Song ◽  
Yonglai Zhang
Keyword(s):  
Delta Sigma Modulator ◽  
Delta Sigma

A Wideband Continuous Time Quadrature Delta Sigma Modulator Based on a Real DSM for Low Power WLAN Receiver

2017 ◽  
Vol 27 (03) ◽  
pp. 1850044 ◽  
Author(s):  
Alireza Shamsi ◽  
Esmaeil Najafi Aghdam
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Continuous Time ◽  
Signal To Noise Ratio ◽  
System Level ◽  
Complex Coefficient ◽  
Loop Filter ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Excess Loop Delay

Power consumption and bandwidth are two of the most important parameters in design of low power wideband modulators as power consumption is growing with the increase in bandwidth. In this study, a multi bit wideband low-power continuous time feed forward quadrature delta sigma modulator (CT-FF-QDSM) is designed for WLAN receiver applications by eliminating adders from modulator structure. In this method, a real modulator is designed and its excess loop delay (ELD) is compensated, then, it is converted into a quadrature structure by applying the complex coefficient to loop filter. Complex coefficients are extracted by the aid of a genetic algorithm to further improve signal to noise ratio (SNR) for bandwidth. One of the disadvantages of CT-FF-QDSM is the adders of loop filters which are power hungry and reduce the effective loop gain. Therefore, the adders have been eliminated while the transfer function is intact in the final modulator. The system level SNR of the proposed modulator is 62.53[Formula: see text]dB using OSR of 12. The circuit is implemented in CMOSTSMC180nm technology. The circuit levels SNR and power consumption are 54[Formula: see text]dB and 13.5[Formula: see text]mW, respectively. Figure of Merit (FOM) obtained from the proposed modulator is about 0.824 (pj/conv) which is improved (by more than 40%) compared to the previous designs.

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