A new technique is proposed for simultaneous, in-situ characterization of in-package thermal resistances (junction-to-case and junction-to-board) in a single test. A thin resistive heater is patterned on package top surface to establish one-dimensional heat conduction along the package vertical direction. Accompanying temperature rise at the heater is measured using a thermocouple and analyzed to estimate equivalent thermal R-C network model of the package. Due to the one-dimensionality of the probing thermal wave, the derived R-C network model represents physical package thermal structure, enabling simultaneous estimation of both thermal resistances (theta-JC and theta-JB). The proposed technique is validated by measuring theta-JC and JB of an overmolded flip-chip ball grid array package. The proposed method eliminates need for a separate test setup for the characterization of each thermal resistance, enhancing the accuracy and efficiency of the package thermal characterization. In addition, use of the external heater and sensing element, instead of on-chip heater and temperature sensor, enables in-situ thermal characterization of a real package mounted on the set board.
