Thermal Performance of LED Filament in Flip-Chip Packaging Manufactured for Different Correlated Color Temperature

The effect of correlated color temperature (CCT) on the thermal performance of light emitting diode (LED) filament in flip-chip packaging was investigated in detail. Two filaments with different lengths were selected as the research object, and the thermal resistance of filaments under three CCT (2200 K, 2400 K, 2700 K) were studied. The optical properties and thermal parameters of the two groups of filaments were measured, and the results were analyzed combined with the color coordinate. The experimental results show that thermal properties of LED filaments is closely related to CCT. Under constant current condition, junction temperature decreases with the increase of color difference. With the change of phosphor glue and phosphorus powder ratio, the color temperature of LED filament also changes. In the filaments with the same chip structure and packaging mechanism, the higher the proportion of red phosphorescent powder, the worse the heat dissipation performance of the filament. These results show that in the design and manufacture of LED filament, it is helpful to control the CCT of LED filament under the premise of meeting the use requirements.

Influence of copper pillar bump structure on flip chip packaging during reflow soldering: a numerical approach

Purpose The purpose of this paper is to present the experimental and simulation studies on the influence of copper pillar bump structure on flip chip packaging during reflow soldering. Design/methodology/approach In this work, solidification/melting modelling and volume of fluid modelling were used. Reflow soldering process of Cu pillar type FC was modelled using computational fluid dynamic software (FLUENT). The experimental results have been validated with the simulation results to prove the accuracy of the numerical method. Findings The findings of this study reveal that solder volume is the most important element influencing reflow soldering. The solder cap volume reduces as the Cu pillar bump diameter lowers, making the reflow process more difficult to establish a good solder union, as less solder is allowed to flow. Last but not least, the solder cap height for the reflow process must be optimized to enable proper solder joint formation. Practical implications This study provides a basis and insights into the impact of copper pillar bump structure on flip chip packaging during reflow soldering that will be advancing the future design of 3D stack package. This study also provides a superior visualization and knowledge of the melting and solidification phenomenon during the reflow soldering process. Originality/value The computational fluid dynamics analysis of copper pillar bump structure on flip chip packaging during reflow soldering is scant. To the authors’ best knowledge, no research has been concentrated on copper pillar bump size configurations in a thorough manner. Without the in-depth study, copper pillar bump size might have the impact of copper pillar bump structure on flip chip packaging during reflow soldering. Five design of parameter of flip chip IC package model was proposed for the investigation of copper pillar bump structure on flip chip packaging during reflow soldering.

A Surface Energy Approach to Developing an Analytical Model for the Underfill Flow Process in Flip-Chip Packaging

This paper presents a new approach to formulating an analytical model for the underfill process in flip-chip packaging to predict the flow front and the filling time. The new approach is based on the concept of surface energy along with the energy conservation principle. This approach avoids the need of modeling the flow path to predict the flow front and the filling time and thus it is suitable to different configurations of solder bumps, including different shapes and arrangements of solder bumps in flip-chip packaging. An experiment along with the CFD simulation was performed based on a proprietarily developed testbed to verify the effectiveness of this approach. Both the experimental and simulation results show that the proposed approach along with its model is accurate for flip-chip packages with different configurations besides the configuration of a regular triangle arrangement of solder bumps and a spherical shape of the solder bump.

A Novel Deprocessing Technique for Revealing Transistor-Level Damage on 7nm FinFET Devices

Physical FA innovations in advanced flip-chip devices are essential, especially for die-level defects. Given the increasing number of metal layers, traditional front-side deprocessing requires a lot of work on parallel lapping and wet etching before reaching the transistor level. Therefore, backside deprocessing is often preferred for checking transistor-level defects, such as subtle ESD damage. This paper presents an efficient technique that involves precise, automated die thinning (from 760µm to 5µm), high-resolution fault localization using a solid immersion lens, and rigorous KOH etch. Using this technique, transistor-level damage was revealed on advanced 7nm FinFET devices with flip-chip packaging.