Optimization of a 0.6μm, single polysilicon emitter bipolar technology versus narrow emitter effects

2002 ◽  
Vol 33 (8) ◽  
pp. 659-665
Author(s):  
M Ullán ◽  
M Lozano ◽  
J Santander ◽  
E Lora-Tamayo ◽  
S Nigrin
Keyword(s):  
Bipolar Technology ◽  
Polysilicon Emitter

Interface Oxide Free Poly Silicon Deposition Using in-Situ HF Cleaning Process

1990 ◽  
Vol 182 ◽  
Author(s):  
C.K. Huang ◽  
A. Feygenson
Keyword(s):  
High Speed ◽  
Cleaning Process ◽  
Auger Analysis ◽  
Impurity Segregation ◽  
Mos Devices ◽  
Bipolar Technology ◽  
Short Time ◽  
Polysilicon Emitter ◽  
Silicon Interface

AbstractA LPCVD polysilicon deposition with in-situ anhydrous HF cleaning process has been developed. The deposited polysilicon and interface properties have been characterized using SIMS, XTEM, RBS, and Auger analysis. The results indicate that an interface oxide free polysilicon deposition using conventional LPCVD furnace can be achieved by careful design of in-situ anhydrous HF cleaning process. After short time rapid thermal annealing, random and channel RBS studies show that most of the deposited polysilicon is epitaxially aligned with silicon substrate and there is no oxide ball up phenomenon. Twinning structure was observed under TEM. No impurity segregation at the poly-mono silicon interface confirms that the interface is oxide free. Possible applications of this polysilicon process include polysilicon emitter contact for high speed bipolar technology and source/drain contacts for MOS devices.

Polycrystalline Silicon in ULSI Technologies: Challenges for Deep-Submicron Structures

1990 ◽  
Vol 182 ◽  
Author(s):  
Catherine Y. Wong ◽  
Tak H. Ning
Keyword(s):  
Deep Submicron ◽  
Basic Material ◽  
Full Potential ◽  
Technology Scaling ◽  
Process Characteristics ◽  
Bipolar Technology ◽  
Device Structures ◽  
Submicron Structures ◽  
Polysilicon Emitter ◽  
Integrated Device

AbstractPolysilicon is a key material widely used in MOSFET, bipolar, and BICMOS devices. As these technologies evolve into the deep submicron regime, several issues emerge in the applications of polysilicon that must be addressed. In sub-0.5µm MOSFET, fabrication and reliability of n + poly for NMOS and p + poly for PMOS should be studied. In bipolar technology, scaling limits of polysilicon emitter must be investigated. Understanding polysilicon, both in terms of its basic material and process characteristics and its characteristics in specific integrated process and/or integrated device structures, is definitely required in order to realize the full potential of ULSI technologies.

Erratum: 24 Gbit/s regenerating demultiplexer IC in silicon bipolar technology

1991 ◽  
Vol 27 (9) ◽  
pp. 787
Author(s):  
J. Hauenschild ◽  
H.-M. Rein ◽  
W. McFarland ◽  
D. Pettengill
Keyword(s):  
Bipolar Technology ◽  
Silicon Bipolar Technology

Selective-Polysilicon Emitter, Self-Aligned Bipolar Structure for BiCMOS VLSI Applications

2005 ◽  
Author(s):  
Shih Wei Sun ◽  
D. Denning ◽  
J. Hayden ◽  
M. Woo ◽  
J. Fitch
Keyword(s):  
Bipolar Structure ◽  
Polysilicon Emitter
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