Polycrystalline Silicon in ULSI Technologies: Challenges for Deep-Submicron Structures

MRS Proceedings ◽

10.1557/proc-182-259 ◽

1990 ◽

Vol 182 ◽

Author(s):

Catherine Y. Wong ◽

Tak H. Ning

Keyword(s):

Deep Submicron ◽

Basic Material ◽

Full Potential ◽

Technology Scaling ◽

Process Characteristics ◽

Bipolar Technology ◽

Device Structures ◽

Submicron Structures ◽

Polysilicon Emitter ◽

Integrated Device

AbstractPolysilicon is a key material widely used in MOSFET, bipolar, and BICMOS devices. As these technologies evolve into the deep submicron regime, several issues emerge in the applications of polysilicon that must be addressed. In sub-0.5µm MOSFET, fabrication and reliability of n + poly for NMOS and p + poly for PMOS should be studied. In bipolar technology, scaling limits of polysilicon emitter must be investigated. Understanding polysilicon, both in terms of its basic material and process characteristics and its characteristics in specific integrated process and/or integrated device structures, is definitely required in order to realize the full potential of ULSI technologies.

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DeepScaleTool : A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401196 ◽

2021 ◽

Author(s):

Satyabrata Sarangi ◽

Bevan Baas

Keyword(s):

Deep Submicron ◽

Accurate Estimation ◽

Technology Scaling

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ACUTE: a high performance analog complementary polysilicon emitter bipolar technology utilizing SOI/trench full dielectric isolation

Proceedings of 1993 IEEE International SOI Conference ◽

10.1109/soi.1993.344573 ◽

2002 ◽

Cited By ~ 5

Author(s):

R.C. Jerome ◽

I.R.C. Post ◽

T.G. Travnicek ◽

G.M. Wodek ◽

K.E. Huffstater ◽

...

Keyword(s):

High Performance ◽

Bipolar Technology ◽

Polysilicon Emitter

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Al reflow studies for deep-submicron structures: properties and microstructure

10.1109/mam.1997.621066 ◽

1997 ◽

Author(s):

M.N. Webster ◽

A.G. Dirks

Keyword(s):

Deep Submicron ◽

Submicron Structures

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The effect of topographical local charging on the etching of deep-submicron structures in SiO2 as a function of aspect ratio

Applied Physics Letters ◽

10.1063/1.1347021 ◽

2001 ◽

Vol 78 (7) ◽

pp. 883-885 ◽

Cited By ~ 70

Author(s):

Jun Matsui ◽

Nobuhiko Nakano ◽

Zoran Lj. Petrović ◽

Toshiaki Makabe

Keyword(s):

Aspect Ratio ◽

Deep Submicron ◽

Submicron Structures

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Non Destructive Nanoparticle Removal from Submicron Structures Using Megasonic Cleaning

Solid State Phenomena ◽

10.4028/www.scientific.net/ssp.195.191 ◽

2012 ◽

Vol 195 ◽

pp. 191-194 ◽

Cited By ~ 1

Author(s):

Pegah Karimi ◽

Ahmed A. Busnaina ◽

Bong Kyun Kang ◽

Jin Goo Park

Keyword(s):

Semiconductor Industry ◽

Acoustic Streaming ◽

Nanoscale Device ◽

Megasonic Cleaning ◽

Nanoscale Particles ◽

Poly Silicon ◽

Patterned Wafers ◽

Device Structures ◽

Submicron Structures ◽

New Generation

The removal of nanoparticles from patterned wafers is one of the main challenges facing the semiconductor industry. As the size of structures shrinks with each new generation of devices, it becomes more difficult to remove nanoscale particles. Nanostructures (specially, poly silicon lines) were found to be vulnerable to damage as a result of cavitation when megasocnic cleaning is utilized. Megasonics utilizes acoustic streaming to reduce the acoustic boundary layer and utilize the generated pulsating flow to remove nanoscale particles from trenches and other structures on the wafer. Although Megasonics is believed to be a solution for many of these cleaning challenges, it has been shown to cause damage to nanoscale device structures such as poly-silicon lines.

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Deep-submicron structures in YBCO: fabrication and measurements

IEEE Transactions on Applied Superconductivity ◽

10.1109/77.402838 ◽

1995 ◽

Vol 5 (2) ◽

pp. 1448-1451 ◽

Cited By ~ 8

Author(s):

A.J.M. van der Harg ◽

E. van der Drift ◽

P. Hadley

Keyword(s):

Deep Submicron ◽

Submicron Structures

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Interface Oxide Free Poly Silicon Deposition Using in-Situ HF Cleaning Process

MRS Proceedings ◽

10.1557/proc-182-9 ◽

1990 ◽

Vol 182 ◽

Author(s):

C.K. Huang ◽

A. Feygenson

Keyword(s):

High Speed ◽

Cleaning Process ◽

Auger Analysis ◽

Impurity Segregation ◽

Mos Devices ◽

Bipolar Technology ◽

Short Time ◽

Polysilicon Emitter ◽

Silicon Interface

AbstractA LPCVD polysilicon deposition with in-situ anhydrous HF cleaning process has been developed. The deposited polysilicon and interface properties have been characterized using SIMS, XTEM, RBS, and Auger analysis. The results indicate that an interface oxide free polysilicon deposition using conventional LPCVD furnace can be achieved by careful design of in-situ anhydrous HF cleaning process. After short time rapid thermal annealing, random and channel RBS studies show that most of the deposited polysilicon is epitaxially aligned with silicon substrate and there is no oxide ball up phenomenon. Twinning structure was observed under TEM. No impurity segregation at the poly-mono silicon interface confirms that the interface is oxide free. Possible applications of this polysilicon process include polysilicon emitter contact for high speed bipolar technology and source/drain contacts for MOS devices.

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