Noise optimisation for the design of a reliable high speed X-ray readout integrated circuit

2000 ◽  
Vol 40 (11) ◽  
pp. 1937-1942 ◽  
Author(s):  
E.F. Tsakas ◽  
A.N. Birbas
2022 ◽  
Vol 17 (01) ◽  
pp. C01036
Author(s):  
P. Grybos ◽  
R. Kleczek ◽  
P. Kmon ◽  
A. Krzyzanowska ◽  
P. Otfinowski ◽  
...  

Abstract This paper presents a readout integrated circuit (IC) of pixel architecture called MPIX (Multithreshold PIXels), designed for CdTe pixel detectors used in X-ray imaging applications. The MPIX IC area is 9.6 mm × 20.3 mm and it is designed in a CMOS 130 nm process. The IC core is a matrix of 96 × 192 square-shaped pixels of 100 µm pitch. Each pixel contains a fast analog front-end followed by four independently working discriminators and four 12-bit ripple counters. Such pixel architecture allows photon processing one by one and selecting the X-ray photons according to their energy (X-ray colour imaging). To fit the different range of applications the MPIX IC has 8 possible different gain settings, and it can process the X-ray photons of energy up to 154 keV. The MPIX chip is bump-bonded to the CdTe 1.5 mm thick pixel sensor with a pixel pitch of 100 µm. To deal with the charge sharing effect coming from a thick semiconductor pixel sensor, multithreshold pattern recognition algorithm is implemented in the readout IC. The implemented algorithm operates both in the analog domain (to recover the total charge spread between neighboring pixels, when a single X-ray photon hits the border of the pixel) and in the digital domain (to allocate a hit position to a single pixel).


2013 ◽  
Vol 22 (09) ◽  
pp. 1340015 ◽  
Author(s):  
YAJING ZHANG ◽  
WENGAO LU ◽  
GUANNAN WANG ◽  
ZHONGJIAN CHEN ◽  
YACONG ZHANG

A readout integrated circuit (ROIC) of infrared focal plane array (IRFPA) with low power and low noise is presented in this paper. It consists of a 384 × 288 pixel array and column-level A/D conversion circuits. The proposed system has high resolution because of the odd–even Analog to Digital Conversion (ADC) structure, containing correlated switches design, multi-Vth amplifier design and high speed high resolution comparator design including latch-stage. Designed and simulated in 0.35-μm CMOS process, this high performance ROIC achieves 81.24 dB SNR at 8.64 KS/s consuming 98 mW under 5 V voltage supply, resulting in an ENOB of 13.2-bit.


2013 ◽  
Vol 718-720 ◽  
pp. 1100-1103
Author(s):  
Liu Dan ◽  
Gao Feng ◽  
Jin Chuan

The test method of 32 channel X-ray readout integrated circuit (ROIC) has been proposed in this paper. Large resistors and a voltage source with high accuracy are used to generate 32 channels of weak currents, which are injected into the ROIC. Some key parameters of ROIC such as linearity, uniformity, cross talk, dynamic range have been tested. This method helps to test ROICs performance and does not need any photodiode and any laser light, which is convenient and easy to be realized.


2004 ◽  
Author(s):  
Eric J. Beuville ◽  
Mark Belding ◽  
Adrienne N. Costello ◽  
Randy Hansen ◽  
Susan M. Petronio

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