A high performance, low-noise 128-channel readout integrated circuit for instrumentation and X-ray applications

A readout integrated circuit (ROIC) of infrared focal plane array (IRFPA) with low power and low noise is presented in this paper. It consists of a 384 × 288 pixel array and column-level A/D conversion circuits. The proposed system has high resolution because of the odd–even Analog to Digital Conversion (ADC) structure, containing correlated switches design, multi-Vth amplifier design and high speed high resolution comparator design including latch-stage. Designed and simulated in 0.35-μm CMOS process, this high performance ROIC achieves 81.24 dB SNR at 8.64 KS/s consuming 98 mW under 5 V voltage supply, resulting in an ENOB of 13.2-bit.

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Pixel readout IC for CdTe detectors operating in single photon counting mode with interpixel communication

Journal of Instrumentation ◽

10.1088/1748-0221/17/01/c01036 ◽

2022 ◽

Vol 17 (01) ◽

pp. C01036

Author(s):

P. Grybos ◽

R. Kleczek ◽

P. Kmon ◽

A. Krzyzanowska ◽

P. Otfinowski ◽

...

Keyword(s):

Integrated Circuit ◽

Single Photon ◽

Photon Counting ◽

Recognition Algorithm ◽

Total Charge ◽

Readout Integrated Circuit ◽

Single Photon Counting ◽

X Ray ◽

Pixel Detectors ◽

Photon Counting Mode

Abstract This paper presents a readout integrated circuit (IC) of pixel architecture called MPIX (Multithreshold PIXels), designed for CdTe pixel detectors used in X-ray imaging applications. The MPIX IC area is 9.6 mm × 20.3 mm and it is designed in a CMOS 130 nm process. The IC core is a matrix of 96 × 192 square-shaped pixels of 100 µm pitch. Each pixel contains a fast analog front-end followed by four independently working discriminators and four 12-bit ripple counters. Such pixel architecture allows photon processing one by one and selecting the X-ray photons according to their energy (X-ray colour imaging). To fit the different range of applications the MPIX IC has 8 possible different gain settings, and it can process the X-ray photons of energy up to 154 keV. The MPIX chip is bump-bonded to the CdTe 1.5 mm thick pixel sensor with a pixel pitch of 100 µm. To deal with the charge sharing effect coming from a thick semiconductor pixel sensor, multithreshold pattern recognition algorithm is implemented in the readout IC. The implemented algorithm operates both in the analog domain (to recover the total charge spread between neighboring pixels, when a single X-ray photon hits the border of the pixel) and in the digital domain (to allocate a hit position to a single pixel).

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A 24.88 nV/√Hz Wheatstone Bridge Readout Integrated Circuit with Chopper-Stabilized Multipath Operational Amplifier

Applied Sciences ◽

10.3390/app10010399 ◽

2020 ◽

Vol 10 (1) ◽

pp. 399 ◽

Cited By ~ 1

Author(s):

Kwonsang Han ◽

Hyungseup Kim ◽

Jaesung Kim ◽

Donggeun You ◽

Hyunwoo Heo ◽

...

Keyword(s):

Integrated Circuit ◽

Operational Amplifier ◽

Wheatstone Bridge ◽

Input Resistance ◽

Cmos Technology ◽

Low Noise ◽

Oxide Semiconductor ◽

Instrumentation Amplifier ◽

Readout Integrated Circuit ◽

Chopper Stabilization

This paper proposes a low noise readout integrated circuit (IC) with a chopper-stabilized multipath operational amplifier suitable for a Wheatstone bridge sensor. The input voltage of the readout IC changes due to a change in input resistance, and is efficiently amplified using a three-operational amplifier instrumentation amplifier (IA) structure with high input impedance and adjustable gain. Furthermore, a chopper-stabilized multipath structure is applied to the operational amplifier, and a ripple reduction loop (RRL) in the low frequency path (LFP) is employed to attenuate the ripple generated by the chopper stabilization technique. A 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) is employed to convert the output voltage of the three-operational amplifier IA into digital code. The Wheatstone bridge readout IC is manufactured using a standard 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology, drawing 833 µA current from a 1.8 V supply. The input range and the input referred noise are ±20 mV and 24.88 nV/√Hz, respectively.

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A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

Journal of Circuits System and Computers ◽

10.1142/s0218126613400331 ◽

2013 ◽

Vol 22 (10) ◽

pp. 1340033 ◽

Cited By ~ 2

Author(s):

HONGLIANG ZHAO ◽

YIQIANG ZHAO ◽

YIWEI SONG ◽

JUN LIAO ◽

JUNFENG GENG

Keyword(s):

Power Consumption ◽

Low Power ◽

Integrated Circuit ◽

High Performance ◽

Supply Voltage ◽

Cmos Technology ◽

High Gain ◽

Readout Integrated Circuit ◽

Chip Area ◽

Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

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